📄 pipemult_lc_new.map.rpt
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; SATURATE_PIPELINE_CLEAR ; none ; Untyped ;
; MULTABSATURATE_PIPELINE_CLEAR ; NONE ; Untyped ;
; MULTCDSATURATE_PIPELINE_CLEAR ; NONE ; Untyped ;
; ZEROACC_PIPELINE_CLEAR ; NONE ; Untyped ;
; SIGNA_PIPELINE_CLEAR ; NONE ; Untyped ;
; SIGNB_PIPELINE_CLEAR ; NONE ; Untyped ;
; MODE0_CLOCK ; none ; Untyped ;
; MODE1_CLOCK ; none ; Untyped ;
; ZEROACC1_CLOCK ; none ; Untyped ;
; SATURATE1_CLOCK ; none ; Untyped ;
; OUTPUT1_CLOCK ; none ; Untyped ;
; OUTPUT2_CLOCK ; none ; Untyped ;
; OUTPUT3_CLOCK ; none ; Untyped ;
; OUTPUT4_CLOCK ; none ; Untyped ;
; OUTPUT5_CLOCK ; none ; Untyped ;
; OUTPUT6_CLOCK ; none ; Untyped ;
; OUTPUT7_CLOCK ; none ; Untyped ;
; MODE0_CLEAR ; none ; Untyped ;
; MODE1_CLEAR ; none ; Untyped ;
; ZEROACC1_CLEAR ; none ; Untyped ;
; SATURATE1_CLEAR ; none ; Untyped ;
; OUTPUT1_CLEAR ; none ; Untyped ;
; OUTPUT2_CLEAR ; none ; Untyped ;
; OUTPUT3_CLEAR ; none ; Untyped ;
; OUTPUT4_CLEAR ; none ; Untyped ;
; OUTPUT5_CLEAR ; none ; Untyped ;
; OUTPUT6_CLEAR ; none ; Untyped ;
; OUTPUT7_CLEAR ; none ; Untyped ;
; MODE0_PIPELINE_CLOCK ; none ; Untyped ;
; MODE1_PIPELINE_CLOCK ; none ; Untyped ;
; ZEROACC1_PIPELINE_CLOCK ; none ; Untyped ;
; SATURATE1_PIPELINE_CLOCK ; none ; Untyped ;
; MODE0_PIPELINE_CLEAR ; none ; Untyped ;
; MODE1_PIPELINE_CLEAR ; none ; Untyped ;
; ZEROACC1_PIPELINE_CLEAR ; none ; Untyped ;
; SATURATE1_PIPELINE_CLEAR ; none ; Untyped ;
; DATAA_FORCED_TO_ZERO ; NO ; Untyped ;
; DATAC_FORCED_TO_ZERO ; NO ; Untyped ;
; USING_ROUNDING ; NO ; Untyped ;
; USING_SATURATION ; NO ; Untyped ;
; USING_MULT_SATURATION ; YES ; Untyped ;
; USING_LOADABLE_ACCUM ; NO ; Untyped ;
; LOADABLE_ACCUM_SUPPORTED ; YES ; Untyped ;
+-------------------------------+-------------+---------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------------+
; lpm_mult Parameter Settings by Entity Instance ;
+---------------------------------------+---------------------------------------+
; Name ; Value ;
+---------------------------------------+---------------------------------------+
; Number of entity instances ; 1 ;
; Entity Instance ; mult:inst|lpm_mult:lpm_mult_component ;
; -- LPM_WIDTHA ; 8 ;
; -- LPM_WIDTHB ; 8 ;
; -- LPM_WIDTHP ; 16 ;
; -- LPM_REPRESENTATION ; UNSIGNED ;
; -- INPUT_A_IS_CONSTANT ; NO ;
; -- INPUT_B_IS_CONSTANT ; NO ;
; -- USE_EAB ; OFF ;
; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ;
; -- INPUT_A_FIXED_VALUE ; Bx ;
; -- INPUT_B_FIXED_VALUE ; Bx ;
+---------------------------------------+---------------------------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult_lc_new.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Mon May 30 09:12:46 2005
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off pipemult -c pipemult_lc_new
Info: Found 2 design units, including 1 entities, in source file ram.vhd
Info: Found design unit 1: ram-rtl
Info: Found entity 1: ram
Info: Found 1 design units, including 1 entities, in source file pipemult.bdf
Info: Found entity 1: pipemult
Info: Elaborating entity "pipemult" for the top level hierarchy
Info: Elaborating entity "ram" for hierarchy "ram:inst1"
Info: Using design file mult.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: mult
Info: Elaborating entity "mult" for hierarchy "mult:inst"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_mult.tdf
Info: Found entity 1: lpm_mult
Info: Elaborating entity "lpm_mult" for hierarchy "mult:inst|lpm_mult:lpm_mult_component"
Info: Found 1 design units, including 1 entities, in source file db/mult_0cr.tdf
Info: Found entity 1: mult_0cr
Info: Elaborating entity "mult_0cr" for hierarchy "mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated"
Warning: Created node "ram:inst1|ram_block~5" as a RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Functionality may differ from the original design
Info: Inferred 1 megafunctions from design logic
Info: Inferred altsyncram megafunction (NUMWORDS_A=32, WIDTH_A=16) from the following design logic: "ram:inst1|ram_block~5"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf
Info: Found entity 1: altsyncram
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_1p51.tdf
Info: Found entity 1: altsyncram_1p51
Info: Converted 1 DSP block slices
Info: Used 1 DSP blocks before DSP block balancing
Info: Used 1 DSP block slices in "Simple Multiplier (9-bit)" mode implemented in approximately 1 DSP blocks
Info: Converted the following 1 DSP block slices to logic elements
Info: DSP block slice in "Simple Multiplier (9-bit)" mode with output node "mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|mac_out1"
Info: DSP block output node "mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|mac_out1"
Info: DSP block multiplier node "mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|mac_mult2"
Info: Used 0 DSP blocks after DSP block balancing
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/alt_mac_mult.tdf
Info: Found entity 1: alt_mac_mult
Info: Issued messages during elaboration of megafunction "mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2"
Warning: Variable or input pin "round_sum" is defined but never used
Info: Found 1 design units, including 1 entities, in source file db/mult_tf71.tdf
Info: Found entity 1: mult_tf71
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/alt_mac_out.tdf
Info: Found entity 1: alt_mac_out
Info: Ignored 82 buffer(s)
Info: Ignored 82 SOFT buffer(s)
Info: Implemented 150 device resources after synthesis - the final resource count might be different
Info: Implemented 28 input pins
Info: Implemented 16 output pins
Info: Implemented 90 logic cells
Info: Implemented 16 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
Info: Processing ended: Mon May 30 09:12:49 2005
Info: Elapsed time: 00:00:04
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