counter_cyclone.qsf

使用Quartus II 5.0开发指导手册

# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:46:55  JANUARY 28, 2004"
set_global_assignment -name LAST_QUARTUS_VERSION 4.0

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_K5 -to CLOCK
set_location_assignment PIN_V7 -to one_seg\[0\]
set_location_assignment PIN_T8 -to one_seg\[1\]
set_location_assignment PIN_R7 -to one_seg\[2\]
set_location_assignment PIN_Y7 -to one_seg\[3\]
set_location_assignment PIN_W7 -to one_seg\[4\]
set_location_assignment PIN_V6 -to one_seg\[5\]
set_location_assignment PIN_U6 -to one_seg\[6\]
set_location_assignment PIN_C4 -to Reset
set_location_assignment PIN_W6 -to ten_seg\[0\]
set_location_assignment PIN_T7 -to ten_seg\[1\]
set_location_assignment PIN_T6 -to ten_seg\[2\]
set_location_assignment PIN_W5 -to ten_seg\[3\]
set_location_assignment PIN_V5 -to ten_seg\[4\]
set_location_assignment PIN_U5 -to ten_seg\[5\]
set_location_assignment PIN_T5 -to ten_seg\[6\]

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 400
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name TOP_LEVEL_ENTITY COUNTER

# Fitter Assignments
# ==================
set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name DEVICE EP1C20F400C7

# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"

# ---------------------------------------
# start EDA_TOOL_SETTINGS(eda_simulation)

	# EDA Netlist Writer Assignments
	# ==============================
	set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION OFF -section_id eda_simulation
	set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS OFF -section_id eda_simulation
	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation

# end EDA_TOOL_SETTINGS(eda_simulation)
# -------------------------------------