counter.vhd

使用Quartus II 5.0开发指导手册

-----------------------------------------
--    Quartus II TECHNICAL TRAINING    --
--    	       counter.vhd             --
-----------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity COUNTER is
port(
	CLOCK   : in std_logic;
	RESET   : in std_logic;
	ONE_SEG : out std_logic_vector(6 downto 0);
	TEN_SEG : out std_logic_vector(6 downto 0));
end entity COUNTER;		 

architecture rtl of COUNTER is

	signal CNT_ONE            : std_logic_vector(3 downto 0); -- counter 0 to 9 for the units
	signal CNT_TEN            : std_logic_vector(3 downto 0); -- counter 0 to 9 for the tenth
	signal CNT_ONE_EQUAL_NINE : std_logic; 
	signal CNT_TEN_EQUAL_NINE : std_logic;
	signal CNT_ONE_ENABLE     : std_logic;
	signal CNT_TEN_ENABLE     : std_logic;

	signal PRESCALER		 			: std_logic_vector(24 downto 0);

begin

	
	--------- COUNTER FOR THE UNITS ----------
	
	CNT_ONE_EQUAL_NINE <= '1' when CNT_ONE = 9  else '0';
	
	counter_unit : process (CLOCK)
	begin
		if rising_edge (CLOCK) then
			if RESET = '0' then
				CNT_ONE <= (others =>'0');
			end if;			
			if CNT_ONE_EQUAL_NINE = '1' and CNT_ONE_ENABLE = '1' then
				CNT_ONE <= (others =>'0');
			elsif CNT_ONE_ENABLE = '1' then 
				CNT_ONE <= CNT_ONE + '1';	
			end if; 
		end if;
	end process;	
	------------------------------------------
	
	--------- COUNTER FOR THE TENTH ----------
	
	CNT_TEN_EQUAL_NINE <= '1' when CNT_TEN = 9   else '0';
	CNT_TEN_ENABLE     <= '1' when CNT_ONE_EQUAL_NINE = '1' AND CNT_ONE_ENABLE = '1' else '0';
	
	counter_tenth : process (CLOCK)
	begin
		if rising_edge(CLOCK) then
			if RESET = '0' then
				CNT_TEN <= (others =>'0');
			end if;	
			if CNT_TEN_EQUAL_NINE = '1' and CNT_TEN_ENABLE = '1' then
				CNT_TEN <= (others => '0'); 
			elsif CNT_TEN_ENABLE = '1' then 
				CNT_TEN <= CNT_TEN + '1';
			end if;				
		end if;
	end process;
	------------------------------------------	
	
	------- COUNTER UNITS'S ENABLE -----------			
	decounter : process (CLOCK)
	begin
		if rising_edge(CLOCK) then
			if RESET = '0' then
				PRESCALER <= (others => '0');
			elsif PRESCALER = "1000000000000000000000000" then
				PRESCALER <= (others => '0');
			else
				PRESCALER <= PRESCALER + '1';	
			end if; 
			if PRESCALER = "1000000000000000000000000" then
				CNT_ONE_ENABLE <= '1';
			else
				CNT_ONE_ENABLE <= '0';
			end if;
		end if;
	end process;

	------------------------------------------	


	--------- DECODER SEGMENT ONE ------------
	decoder_seg_one : process(CNT_ONE)
	begin
		case CNT_ONE is
			when "0000" => ONE_SEG <= "0000001"; 
			when "0001" => ONE_SEG <= "1001111";
			when "0010" => ONE_SEG <= "0010010"; 
			when "0011" => ONE_SEG <= "0000110";
			when "0100" => ONE_SEG <= "1001100"; 
			when "0101" => ONE_SEG <= "0100100";
			when "0110" => ONE_SEG <= "0100000"; 
			when "0111" => ONE_SEG <= "0001111";
			when "1000" => ONE_SEG <= "0000000"; 
			when "1001" => ONE_SEG <= "0000100";	
			when others => ONE_SEG <= "0000000";
		end case;
	end process;	
	------------------------------------------				
			
	--------- DECODER SEGMENT TEN ------------
	decoder_seg_ten : process(CNT_TEN)
	begin
		case CNT_TEN is
			when "0000" => TEN_SEG <= "1111111"; 
			when "0001" => TEN_SEG <= "1001111";
			when "0010" => TEN_SEG <= "0010010"; 
			when "0011" => TEN_SEG <= "0000110";
			when "0100" => TEN_SEG <= "1001100"; 
			when "0101" => TEN_SEG <= "0100100";
			when "0110" => TEN_SEG <= "0100000"; 
			when "0111" => TEN_SEG <= "0001111";
			when "1000" => TEN_SEG <= "0000000"; 
			when "1001" => TEN_SEG <= "0000100";	
			when others => TEN_SEG <= "0000000";
		end case;
	end process;	
	------------------------------------------	

end rtl;