counter.vhd

使用Quartus II 5.0开发指导手册

-----------------------------------------
--    QUARTUS II TECHNICAL TRAINING    --
--       2-Digit Decimal Counter       --
-----------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity COUNTER is
generic
	(
		PRESCALER : integer := 2 -- setS clock divider value to slow 
								 --    high speed input clocks
	);	
port
	(
		CLOCK   : in std_logic;
		RESET   : in std_logic;
		CNT_ONE : out std_logic_vector(3 downto 0); -- counter output for the ones digit
		CNT_TEN : out std_logic_vector(3 downto 0) -- counter output for the tens digit	
     );
end entity COUNTER;		 

architecture rtl of COUNTER is

	signal CNT_ONE_INT		  : integer RANGE 0 to 9;  -- internal ones counter variable
	signal CNT_TEN_INT		  : integer RANGE 0 TO 9;  -- internal tens counter variable
	signal CNT_ONE_EQUAL_NINE : std_logic; 
	signal CNT_TEN_EQUAL_NINE : std_logic;
	signal CNT_ONE_ENABLE     : std_logic;
	signal CNT_TEN_ENABLE     : std_logic;

	signal PRESCALER_TEST     : integer RANGE 0 to PRESCALER-1;

begin

	--------- OUTPUTS ------------------------
	
	CNT_ONE <= conv_std_logic_vector(CNT_ONE_INT,4);
	CNT_TEN <= conv_std_logic_vector(CNT_TEN_INT,4);
	
	------------------------------------------
	
	
	--------- COUNTER FOR THE ONES ----------
	
	CNT_ONE_EQUAL_NINE <= '1' when CNT_ONE_INT = 9  else '0';
	
	counter_unit : process (CLOCK)
	begin
		if rising_edge (CLOCK) then
			if RESET = '0' then
				CNT_ONE_INT <= 0;
			end if;			
			if (CNT_ONE_EQUAL_NINE = '1' and CNT_ONE_ENABLE = '1') then
				CNT_ONE_INT <= 0;
			elsif CNT_ONE_ENABLE = '1' then 
				CNT_ONE_INT <= CNT_ONE_INT + 1;	
			end if; 
		end if;
	end process;	
	-----------------------------------------
	
	--------- COUNTER FOR THE TENS ----------
	
	CNT_TEN_EQUAL_NINE <= '1' when CNT_TEN_INT = 9   else '0';
	CNT_TEN_ENABLE     <= '1' when CNT_ONE_EQUAL_NINE = '1' and CNT_ONE_ENABLE = '1' else '0';
	
	counter_tenth : process (CLOCK)
	begin
		if rising_edge(CLOCK) then
			if RESET = '0' then
				CNT_TEN_INT <= 0;
			end if;	
			if (CNT_ONE_EQUAL_NINE = '1' and CNT_TEN_EQUAL_NINE = '1' and CNT_ONE_ENABLE = '1') then
				CNT_TEN_INT <= 0; 
			elsif CNT_TEN_ENABLE = '1' then 
				CNT_TEN_INT <= CNT_TEN_INT + 1;
			end if;				
		end if;
	end process;
	------------------------------------------	
	
	------- COUNTER UNITS'S ENABLE -----------
	decounter : process (CLOCK)
	begin
		if rising_edge(CLOCK) then
			if RESET = '0' then
				PRESCALER_TEST <= 0;
			elsif PRESCALER = 8388607 then
				PRESCALER_TEST <= 0;
			else
				PRESCALER_TEST <= PRESCALER_TEST + 1;	
			end if; 
			if PRESCALER_TEST = 8388607 then
				CNT_ONE_ENABLE <= '1';
			else
				CNT_ONE_ENABLE <= '0';
			end if;
		end if;
	end process;

	------------------------------------------	

end rtl;