collection.csf.qmsg

该系统是一个实现图像数据采集以及对图像数据的插值处理

{ "Info" "ITAN_NO_REG2REG_EXIST" "frameValid " "Info: No valid register-to-register paths exist for clock frameValid" {  } {  } 0}
{ "Info" "ITDB_TSU_RESULT" "collection_buffer:inst\|y\[4\]~reg0 frameValid lineValid 11.550 ns register " "Info: tsu for register collection_buffer:inst\|y\[4\]~reg0 (data pin = frameValid, clock pin = lineValid) is 11.550 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "19.850 ns + Longest pin register " "Info: + Longest pin to register delay is 19.850 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(10.300 ns) 10.300 ns frameValid 1 CLK Unassigned 8 " "Info: 1: + IC(0.000 ns) + CELL(10.300 ns) = 10.300 ns; Loc. = Unassigned; Fanout = 8; CLK Node = 'frameValid'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "" { frameValid } "NODE_NAME" } } } { "E:/verilog/复件 (2) collection/collection.bdf" "" "" { Schematic "E:/verilog/复件 (2) collection/collection.bdf" { { 160 -112 56 176 "frameValid" "" } { 160 56 56 168 "<<__\$DEF_ALIAS178>>" "" } { 168 56 56 184 "<<__\$DEF_ALIAS50>>" "" } { 184 56 56 200 "<<__\$DEF_ALIAS47>>" "" } { 200 56 56 232 "<<__\$DEF_ALIAS126>>" "" } { 232 56 56 264 "<<__\$DEF_ALIAS139>>" "" } { 144 56 160 160 "<<Link_picture>>" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.360 ns) + CELL(2.700 ns) 13.360 ns collection_buffer:inst\|i18~39 2 COMB Unassigned 8 " "Info: 2: + IC(0.360 ns) + CELL(2.700 ns) = 13.360 ns; Loc. = Unassigned; Fanout = 8; COMB Node = 'collection_buffer:inst\|i18~39'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "3.060 ns" { frameValid collection_buffer:inst|i18~39 } "NODE_NAME" } } } { "E:/verilog/复件 (2) collection/collection_buffer.v" "" "" { Text "E:/verilog/复件 (2) collection/collection_buffer.v" 28 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.240 ns) + CELL(1.400 ns) 15.000 ns collection_buffer:inst\|lpm_add_sub:i_rtl_6\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\] 3 COMB Unassigned 2 " "Info: 3: + IC(0.240 ns) + CELL(1.400 ns) = 15.000 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'collection_buffer:inst\|lpm_add_sub:i_rtl_6\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\]'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "1.640 ns" { collection_buffer:inst|i18~39 collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[0] } "NODE_NAME" } } } { "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.150 ns) + CELL(0.300 ns) 15.450 ns collection_buffer:inst\|lpm_add_sub:i_rtl_6\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\] 4 COMB Unassigned 2 " "Info: 4: + IC(0.150 ns) + CELL(0.300 ns) = 15.450 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'collection_buffer:inst\|lpm_add_sub:i_rtl_6\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\]'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "0.450 ns" { collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[0] collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[1] } "NODE_NAME" } } } { "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.150 ns) + CELL(0.300 ns) 15.900 ns collection_buffer:inst\|lpm_add_sub:i_rtl_6\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\] 5 COMB Unassigned 2 " "Info: 5: + IC(0.150 ns) + CELL(0.300 ns) = 15.900 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'collection_buffer:inst\|lpm_add_sub:i_rtl_6\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\]'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "0.450 ns" { collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[1] collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[2] } "NODE_NAME" } } } { "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.150 ns) + CELL(0.300 ns) 16.350 ns collection_buffer:inst\|lpm_add_sub:i_rtl_6\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\] 6 COMB Unassigned 1 " "Info: 6: + IC(0.150 ns) + CELL(0.300 ns) = 16.350 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'collection_buffer:inst\|lpm_add_sub:i_rtl_6\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\]'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "0.450 ns" { collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[2] collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[3] } "NODE_NAME" } } } { "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.150 ns) + CELL(1.200 ns) 17.700 ns collection_buffer:inst\|lpm_add_sub:i_rtl_6\|addcore:adder\|unreg_res_node\[4\] 7 COMB Unassigned 1 " "Info: 7: + IC(0.150 ns) + CELL(1.200 ns) = 17.700 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'collection_buffer:inst\|lpm_add_sub:i_rtl_6\|addcore:adder\|unreg_res_node\[4\]'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "1.350 ns" { collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[3] collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|unreg_res_node[4] } "NODE_NAME" } } } { "d:/quartus/libraries/megafunctions/addcore.tdf" "" "" { Text "d:/quartus/libraries/megafunctions/addcore.tdf" 95 16 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.150 ns) + CELL(2.000 ns) 19.850 ns collection_buffer:inst\|y\[4\]~reg0 8 REG Unassigned 5 " "Info: 8: + IC(0.150 ns) + CELL(2.000 ns) = 19.850 ns; Loc. = Unassigned; Fanout = 5; REG Node = 'collection_buffer:inst\|y\[4\]~reg0'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "2.150 ns" { collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|unreg_res_node[4] collection_buffer:inst|y[4]~reg0 } "NODE_NAME" } } } { "E:/verilog/复件 (2) collection/collection_buffer.v" "" "" { Text "E:/verilog/复件 (2) collection/collection_buffer.v" 32 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "18.500 ns 93.20 % " "Info: Total cell delay = 18.500 ns ( 93.20 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.350 ns 6.80 % " "Info: Total interconnect delay = 1.350 ns ( 6.80 % )" {  } {  } 0}  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "19.850 ns" { frameValid collection_buffer:inst|i18~39 collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[0] collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[1] collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[2] collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[3] collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|unreg_res_node[4] collection_buffer:inst|y[4]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.600 ns + " "Info: + Micro setup delay of destination is 2.600 ns" {  } { { "E:/verilog/复件 (2) collection/collection_buffer.v" "" "" { Text "E:/verilog/复件 (2) collection/collection_buffer.v" 32 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "lineValid destination 10.900 ns - Shortest register " "Info: - Shortest clock path from clock lineValid to destination register is 10.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(10.300 ns) 10.300 ns lineValid 1 CLK Unassigned 17 " "Info: 1: + IC(0.000 ns) + CELL(10.300 ns) = 10.300 ns; Loc. = Unassigned; Fanout = 17; CLK Node = 'lineValid'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floor