📄 collection.csf.qmsg

📁 该系统是一个实现图像数据采集以及对图像数据的插值处理
💻 QMSG
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{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "lineValid " "Info: Assuming node lineValid is an undefined clock" {  } { { "E:/verilog/复件 (2) collection/collection.bdf" "" "" { Schematic "E:/verilog/复件 (2) collection/collection.bdf" { { 176 -112 56 192 "lineValid" "" } { 160 56 56 168 "<<__\$DEF_ALIAS178>>" "" } { 168 56 56 184 "<<__\$DEF_ALIAS50>>" "" } { 184 56 56 200 "<<__\$DEF_ALIAS47>>" "" } { 200 56 56 232 "<<__\$DEF_ALIAS126>>" "" } { 232 56 56 264 "<<__\$DEF_ALIAS139>>" "" } { 144 56 160 160 "<<Link_picture>>" "" } } } } { "d:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "d:/quartus/bin/Assignment Editor.qase" 1 { { 0 "lineValid" } } } }  } 0} { "Info" "ITDB_NODE_MAP_TO_CLK" "iPixClk " "Info: Assuming node iPixClk is an undefined clock" {  } { { "E:/verilog/复件 (2) collection/collection.bdf" "" "" { Schematic "E:/verilog/复件 (2) collection/collection.bdf" { { 192 -112 56 208 "iPixClk" "" } { 160 56 56 168 "<<__\$DEF_ALIAS178>>" "" } { 168 56 56 184 "<<__\$DEF_ALIAS50>>" "" } { 184 56 56 200 "<<__\$DEF_ALIAS47>>" "" } { 200 56 56 232 "<<__\$DEF_ALIAS126>>" "" } { 232 56 56 264 "<<__\$DEF_ALIAS139>>" "" } { 144 56 160 160 "<<Link_picture>>" "" } } } } { "d:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "d:/quartus/bin/Assignment Editor.qase" 1 { { 0 "iPixClk" } } } }  } 0} { "Info" "ITDB_NODE_MAP_TO_CLK" "frameValid " "Info: Assuming node frameValid is an undefined clock" {  } { { "E:/verilog/复件 (2) collection/collection.bdf" "" "" { Schematic "E:/verilog/复件 (2) collection/collection.bdf" { { 160 -112 56 176 "frameValid" "" } { 160 56 56 168 "<<__\$DEF_ALIAS178>>" "" } { 168 56 56 184 "<<__\$DEF_ALIAS50>>" "" } { 184 56 56 200 "<<__\$DEF_ALIAS47>>" "" } { 200 56 56 232 "<<__\$DEF_ALIAS126>>" "" } { 232 56 56 264 "<<__\$DEF_ALIAS139>>" "" } { 144 56 160 160 "<<Link_picture>>" "" } } } } { "d:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "d:/quartus/bin/Assignment Editor.qase" 1 { { 0 "frameValid" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "lineValid register collection_buffer:inst\|y\[0\]~reg0 register collection_buffer:inst\|y\[4\]~reg0 48.47 MHz 20.63 ns Internal " "Info: Clock lineValid has Internal fmax of 48.47 MHz between source register collection_buffer:inst\|y\[0\]~reg0 and destination register collection_buffer:inst\|y\[4\]~reg0 (period= 20.63 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.630 ns + Longest register register " "Info: + Longest register to register delay is 16.630 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns collection_buffer:inst\|y\[0\]~reg0 1 REG Unassigned 55 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = Unassigned; Fanout = 55; REG Node = 'collection_buffer:inst\|y\[0\]~reg0'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "" { collection_buffer:inst|y[0]~reg0 } "NODE_NAME" } } } { "E:/verilog/复件 (2) collection/collection_buffer.v" "" "" { Text "E:/verilog/复件 (2) collection/collection_buffer.v" 32 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.680 ns) + CELL(2.700 ns) 4.380 ns collection_buffer:inst\|i~29 2 COMB Unassigned 1 " "Info: 2: + IC(1.680 ns) + CELL(2.700 ns) = 4.380 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'collection_buffer:inst\|i~29'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "4.380 ns" { collection_buffer:inst|y[0]~reg0 collection_buffer:inst|i~29 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.150 ns) + CELL(2.700 ns) 7.230 ns collection_buffer:inst\|i~30 3 COMB Unassigned 3 " "Info: 3: + IC(0.150 ns) + CELL(2.700 ns) = 7.230 ns; Loc. = Unassigned; Fanout = 3; COMB Node = 'collection_buffer:inst\|i~30'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "2.850 ns" { collection_buffer:inst|i~29 collection_buffer:inst|i~30 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.210 ns) + CELL(2.700 ns) 10.140 ns collection_buffer:inst\|i18~39 4 COMB Unassigned 8 " "Info: 4: + IC(0.210 ns) + CELL(2.700 ns) = 10.140 ns; Loc. = Unassigned; Fanout = 8; COMB Node = 'collection_buffer:inst\|i18~39'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "2.910 ns" { collection_buffer:inst|i~30 collection_buffer:inst|i18~39 } "NODE_NAME" } } } { "E:/verilog/复件 (2) collection/collection_buffer.v" "" "" { Text "E:/verilog/复件 (2) collection/collection_buffer.v" 28 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.240 ns) + CELL(1.400 ns) 11.780 ns collection_buffer:inst\|lpm_add_sub:i_rtl_6\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\] 5 COMB Unassigned 2 " "Info: 5: + IC(0.240 ns) + CELL(1.400 ns) = 11.780 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'collection_buffer:inst\|lpm_add_sub:i_rtl_6\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\]'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "1.640 ns" { collection_buffer:inst|i18~39 collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[0] } "NODE_NAME" } } } { "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.150 ns) + CELL(0.300 ns) 12.230 ns collection_buffer:inst\|lpm_add_sub:i_rtl_6\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\] 6 COMB Unassigned 2 " "Info: 6: + IC(0.150 ns) + CELL(0.300 ns) = 12.230 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'collection_buffer:inst\|lpm_add_sub:i_rtl_6\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\]'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "0.450 ns" { collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[0] collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[1] } "NODE_NAME" } } } { "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.150 ns) + CELL(0.300 ns) 12.680 ns collection_buffer:inst\|lpm_add_sub:i_rtl_6\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\] 7 COMB Unassigned 2 " "Info: 7: + IC(0.150 ns) + CELL(0.300 ns) = 12.680 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'collection_buffer:inst\|lpm_add_sub:i_rtl_6\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\]'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "0.450 ns" { collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[1] collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[2] } "NODE_NAME" } } } { "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.150 ns) + CELL(0.300 ns) 13.130 ns collection_buffer:inst\|lpm_add_sub:i_rtl_6\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\] 8 COMB Unassigned 1 " "Info: 8: + IC(0.150 ns) + CELL(0.300 ns) = 13.130 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'collection_buffer:inst\|lpm_add_sub:i_rtl_6\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\]'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "0.450 ns" { collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[2] collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[3] } "NODE_NAME" } } } { "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.150 ns) + CELL(1.200 ns) 14.480 ns collection_buffer:inst\|lpm_add_sub:i_rtl_6\|addcore:adder\|unreg_res_node\[4\] 9 COMB Unassigned 1 " "Info: 9: + IC(0.150 ns) + CELL(1.200 ns) = 14.480 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'collection_buffer:inst\|lpm_add_sub:i_rtl_6\|addcore:adder\|unreg_res_node\[4\]'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "1.350 ns" { collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[3] collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|unreg_res_node[4] } "NODE_NAME" } } } { "d:/quartus/libraries/megafunctions/addcore.tdf" "" "" { Text "d:/quartus/libraries/megafunctions/addcore.tdf" 95 16 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.150 ns) + CELL(2.000 ns) 16.630 ns collection_buffer:inst\|y\[4\]~reg0 10 REG Unassigned 5 " "Info: 10: + IC(0.150 ns) + CELL(2.000 ns) = 16.630 ns; Loc. = Unassigned; Fanout = 5; REG Node = 'collection_buffer:inst\|y\[4\]~reg0'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "2.150 ns" { collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|unreg_res_node[4] collection_buffer:inst|y[4]~reg0 } "NODE_NAME" } } } { "E:/verilog/复件 (2) collection/collection_buffer.v" "" "" { Text "E:/verilog/复件 (2) collection/collection_buffer.v" 32 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.600 ns 81.78 % " "Info: Total cell delay = 13.600 ns ( 81.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.030 ns 18.22 % " "Info: Total interconnect delay = 3.030 ns ( 18.22 % )" {  } {  } 0}  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "16.630 ns" { collection_buffer:inst|y[0]~reg0 collection_buffer:inst|i~29 collection_buffer:inst|i~30 collection_buffer:inst|i18~39 collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[0] collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[1] collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[2] collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[3] collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|unreg_res_node[4] collection_buffer:inst|y[4]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "lineValid destination 10.900 ns + Shortest register " "Info: + Shortest clock path from clock lineValid to destination register is 10.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(10.300 ns) 10.300 ns lineValid 1 CLK Unassigned 17 " "Info: 1: + IC(0.000 ns) + CELL(10.300 ns) = 10.300 ns; Loc. = Unassigned; Fanout = 17; CLK Node = 'lineValid'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "" { lineValid } "NODE_NAME" } } } { "E:/verilog/复件 (2) collection/collection.bdf" "" "" { Schematic "E:/verilog/复件 (2) collection/collection.bdf" { { 176 -112 56 192 "lineValid" "" } { 160 56 56 168 "<<__\$DEF_ALIAS178>>" "" } { 168 56 56 184 "<<__\$DEF_ALIAS50>>" "" } { 184 56 56 200 "<<__\$DEF_ALIAS47>>" "" } { 200 56 56 232 "<<__\$DEF_ALIAS126>>" "" } { 232 56 56 264 "<<__\$DEF_ALIAS139>>" "" } { 144 56 160 160 "<<Link_picture>>" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.000 ns) 10.900 ns collection_buffer:inst\|y\[4\]~reg0 2 REG Unassigned 5 " "Info: 2: + IC(0.600 ns) + CELL(0.000 ns) = 10.900 ns; Loc. = Unassigned; Fanout = 5; REG Node = 'collection_buffer:inst\|y\[4\]~reg0'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "0.600 ns" { lineValid collection_buffer:inst|y[4]~reg0 } "NODE_NAME" } } } { "E:/verilog/复件 (2) collection/collection_buffer.v" "" "" { Text "E:/verilog/复件 (2) collection/collection_buffer.v" 32 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.300 ns 94.50 % " "Info: Total cell delay = 10.300 ns ( 94.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns 5.50 % " "Info: Total interconnect delay = 0.600 ns ( 5.50 % )" {  } {  } 0}  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "10.900 ns" { lineValid collection_buffer:inst|y[4]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "lineValid source 10.900 ns - Longest register " "Info: - Longest clock path from clock lineValid to source register is 10.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(10.300 ns) 10.300 ns lineValid 1 CLK Unassigned 17 " "Info: 1: + IC(0.000 ns) + CELL(10.300 ns) = 10.300 ns; Loc. = Unassigned; Fanout = 17; CLK Node = 'lineValid'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "" { lineValid } "NODE_NAME" } } } { "E:/verilog/复件 (2) collection/collection.bdf" "" "" { Schematic "E:/verilog/复件 (2) collection/collection.bdf" { { 176 -112 56 192 "lineValid" "" } { 160 56 56 168 "<<__\$DEF_ALIAS178>>" "" } { 168 56 56 184 "<<__\$DEF_ALIAS50>>" "" } { 184 56 56 200 "<<__\$DEF_ALIAS47>>" "" } { 200 56 56 232 "<<__\$DEF_ALIAS126>>" "" } { 232 56 56 264 "<<__\$DEF_ALIAS139>>" "" } { 144 56 160 160 "<<Link_picture>>" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.000 ns) 10.900 ns collection_buffer:inst\|y\[0\]~reg0 2 REG Unassigned 55 " "Info: 2: + IC(0.600 ns) + CELL(0.000 ns) = 10.900 ns; Loc. = Unassigned; Fanout = 55; REG Node = 'collection_buffer:inst\|y\[0\]~reg0'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "0.600 ns" { lineValid collection_buffer:inst|y[0]~reg0 } "NODE_NAME" } } } { "E:/verilog/复件 (2) collection/collection_buffer.v" "" "" { Text "E:/verilog/复件 (2) collection/collection_buffer.v" 32 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.300 ns 94.50 % " "Info: Total cell delay = 10.300 ns ( 94.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns 5.50 % " "Info: Total interconnect delay = 0.600 ns ( 5.50 % )" {  } {  } 0}  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "10.900 ns" { lineValid collection_buffer:inst|y[0]~reg0 } "NODE_NAME" } } }  } 0}  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "10.900 ns" { lineValid collection_buffer:inst|y[4]~reg0 } "NODE_NAME" } } } { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "10.900 ns" { lineValid collection_buffer:inst|y[0]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.400 ns + " "Info: + Micro clock to output delay of source is 1.400 ns" {  } { { "E:/verilog/复件 (2) collection/collection_buffer.v" "" "" { Text "E:/verilog/复件 (2) collection/collection_buffer.v" 32 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.600 ns + " "Info: + Micro setup delay of destination is 2.600 ns" {  } { { "E:/verilog/复件 (2) collection/collection_buffer.v" "" "" { Text "E:/verilog/复件 (2) collection/collection_buffer.v" 32 -1 0 } }  } 0}  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "16.630 ns" { collection_buffer:inst|y[0]~reg0 collection_buffer:inst|i~29 collection_buffer:inst|i~30 collection_buffer:inst|i18~39 collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[0] collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[1] collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[2] collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[3] collection_buffer:inst|lpm_add_sub:i_rtl_6|addcore:adder|unreg_res_node[4] collection_buffer:inst|y[4]~reg0 } "NODE_NAME" } } } { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "10.900 ns" { lineValid collection_buffer:inst|y[4]~reg0 } "NODE_NAME" } } } { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "10.900 ns" { lineValid collection_buffer:inst|y[0]~reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "iPixClk register collection_buffer:inst\|lpm_counter:x_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] register color_interpolation:inst1\|Red\[6\]~reg0 5.74 MHz 174.08 ns Internal " "Info: Clock iPixClk has Internal fmax of 5.74 MHz between source register collection_buffer:inst\|lpm_counter:x_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] and destination register color_interpolation:inst1\|Red\[6\]~reg0 (period= 174.08 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "83.040 ns + Longest register register " "Info: + Longest register to register delay is 83.040 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns collection_buffer:inst\|lpm_counter:x_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 1 REG Unassigned 103 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = Unassigned; Fanout = 103; REG Node = 'collection_buffer:inst\|lpm_counter:x_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "" { collection_buffer:inst|lpm_counter:x_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } } { "d:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "d:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.090 ns) + CELL(2.700 ns) 5.790 ns color_interpolation:inst1\|i2216~53 2 COMB Unassigned 4 " "Info: 2: + IC(3.090 ns) + CELL(2.700 ns) = 5.790 ns; Loc. = Unassigned; Fanout = 4; COMB Node = 'color_interpolation:inst1\|i2216~53'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "5.790 ns" { collection_buffer:inst|lpm_counter:x_rtl_0|alt_counter_f10ke:wysi_counter|q[3] color_interpolation:inst1|i2216~53 } "NODE_NAME" } } } { "E:/毕业设计/collection/color_interpolation.v" "" "" { Text "E:/毕业设计/collection/color_interpolation.v" 48 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.240 ns) + CELL(2.700 ns) 8.730 ns color_interpolation:inst1\|i2708~19 3 COMB Unassigned 2 " "Info: 3: + IC(0.240 ns) + CELL(2.700 ns) = 8.730 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'color_interpolation:inst1\|i2708~19'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "2.940 ns" { color_interpolation:inst1|i2216~53 color_interpolation:inst1|i2708~19 } "NODE_NAME" } } } { "E:/毕业设计/collection/color_interpolation.v" "" "" { Text "E:/毕业设计/collection/color_interpolation.v" 111 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.180 ns) + CELL(2.400 ns) 11.310 ns color_interpolation:inst1\|i8~21 4 COMB Unassigned 62 " "Info: 4: + IC(0.180 ns) + CELL(2.400 ns) = 11.310 ns; Loc. = Unassigned; Fanout = 62; COMB Node = 'color_interpolation:inst1\|i8~21'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "2.580 ns" { color_interpolation:inst1|i2708~19 color_interpolation:inst1|i8~21 } "NODE_NAME" } } } { "E:/毕业设计/collection/color_interpolation.v" "" "" { Text "E:/毕业设计/collection/color_interpolation.v" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.980 ns) + CELL(2.700 ns) 15.990 ns color_interpolation:inst1\|i2071~44 5 COMB Unassigned 30 " "Info: 5: + IC(1.980 ns) + CELL(2.700 ns) = 15.990 ns; Loc. = Unassigned; Fanout = 30; COMB Node = 'color_interpolation:inst1\|i2071~44'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "4.680 ns" { color_interpolation:inst1|i8~21 color_interpolation:inst1|i2071~44 } "NODE_NAME" } } } { "E:/毕业设计/collection/color_interpolation.v" "" "" { Text "E:/毕业设计/collection/color_interpolation.v" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.020 ns) + CELL(2.700 ns) 19.710 ns color_interpolation:inst1\|i2167~49 6 COMB Unassigned 18 " "Info: 6: + IC(1.020 ns) + CELL(2.700 ns) = 19.710 ns; Loc. = Unassigned; Fanout = 18; COMB Node = 'color_interpolation:inst1\|i2167~49'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "3.720 ns" { color_interpolation:inst1|i2071~44 color_interpolation:inst1|i2167~49 } "NODE_NAME" } } } { "E:/毕业设计/collection/color_interpolation.v" "" "" { Text "E:/毕业设计/collection/color_interpolation.v" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.660 ns) + CELL(2.700 ns) 23.070 ns color_interpolation:inst1\|i2159~0 7 COMB Unassigned 16 " "Info: 7: + IC(0.660 ns) + CELL(2.700 ns) = 23.070 ns; Loc. = Unassigned; Fanout = 16; COMB Node = 'color_interpolation:inst1\|i2159~0'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "3.360 ns" { color_interpolation:inst1|i2167~49 color_interpolation:inst1|i2159~0 } "NODE_NAME" } } } { "E:/毕业设计/collection/color_interpolation.v" "" "" { Text "E:/毕业设计/collection/color_interpolation.v" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.400 ns) 26.070 ns color_interpolation:inst1\|i2166~34 8 COMB Unassigned 1 " "Info: 8: + IC(0.600 ns) + CELL(2.400 ns) = 26.070 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'color_interpolation:inst1\|i2166~34'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "3.000 ns" { color_interpolation:inst1|i2159~0 color_interpolation:inst1|i2166~34 } "NODE_NAME" } } } { "E:/毕业设计/collection/color_interpolation.v" "" "" { Text "E:/毕业设计/collection/color_interpolation.v" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.150 ns) + CELL(2.400 ns) 28.620 ns color_interpolation:inst1\|i~20876 9 COMB Unassigned 1 " "Info: 9: + IC(0.150 ns) + CELL(2.400 ns) = 28.620 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'color_interpolation:inst1\|i~20876'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "2.550 ns" { color_interpolation:inst1|i2166~34 color_interpolation:inst1|i~20876 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.150 ns) + CELL(2.700 ns) 31.470 ns color_interpolation:inst1\|i~20877 10 COMB Unassigned 1 " "Info: 10: + IC(0.150 ns) + CELL(2.700 ns) = 31.470 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'color_interpolation:inst1\|i~20877'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "2.850 ns" { color_interpolation:inst1|i~20876 color_interpolation:inst1|i~20877 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.150 ns) + CELL(2.700 ns) 34.320 ns color_interpolation:inst1\|i~20874 11 COMB Unassigned 1 " "Info: 11: + IC(0.150 ns) + CELL(2.700 ns) = 34.320 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'color_interpolation:inst1\|i~20874'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "2.850 ns" { color_interpolation:inst1|i~20877 color_interpolation:inst1|i~20874 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.150 ns) + CELL(2.700 ns) 37.170 ns color_interpolation:inst1\|i~20875 12 COMB Unassigned 2 " "Info: 12: + IC(0.150 ns) + CELL(2.700 ns) = 37.170 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'color_interpolation:inst1\|i~20875'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "2.850 ns" { color_interpolation:inst1|i~20874 color_interpolation:inst1|i~20875 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.180 ns) + CELL(2.400 ns) 39.750 ns color_interpolation:inst1\|i~20264 13 COMB Unassigned 1 " "Info: 13: + IC(0.180 ns) + CELL(2.400 ns) = 39.750 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'color_interpolation:inst1\|i~20264'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "2.580 ns" { color_interpolation:inst1|i~20875 color_interpolation:inst1|i~20264 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.150 ns) + CELL(2.700 ns) 42.600 ns color_interpolation:inst1\|i~20265 14 COMB Unassigned 2 " "Info: 14: + IC(0.150 ns) + CELL(2.700 ns) = 42.600 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'color_interpolation:inst1\|i~20265'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "2.850 ns" { color_interpolation:inst1|i~20264 color_interpolation:inst1|i~20265 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.180 ns) + CELL(1.700 ns) 44.480 ns color_interpolation:inst1\|i~21724 15 COMB Unassigned 1 " "Info: 15: + IC(0.180 ns) + CELL(1.700 ns) = 44.480 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'color_interpolation:inst1\|i~21724'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "1.880 ns" { color_interpolation:inst1|i~20265 color_interpolation:inst1|i~21724 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.150 ns) + CELL(2.000 ns) 46.630 ns color_interpolation:inst1\|i~21758 16 COMB Unassigned 3 " "Info: 16: + IC(0.150 ns) + CELL(2.000 ns) = 46.630 ns; Loc. = Unassigned; Fanout = 3; COMB Node = 'color_interpolation:inst1\|i~21758'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "2.150 ns" { color_interpolation:inst1|i~21724 color_interpolation:inst1|i~21758 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.210 ns) + CELL(2.700 ns) 49.540 ns color_interpolation:inst1\|lpm_add_sub:i_rtl_8\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~132 17 COMB Unassigned 2 " "Info: 17: + IC(0.210 ns) + CELL(2.700 ns) = 49.540 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'color_interpolation:inst1\|lpm_add_sub:i_rtl_8\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~132'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "2.910 ns" { color_interpolation:inst1|i~21758 color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~132 } "NODE_NAME" } } } { "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.180 ns) + CELL(2.700 ns) 52.420 ns color_interpolation:inst1\|lpm_add_sub:i_rtl_8\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[1\]~130 18 COMB Unassigned 2 " "Info: 18: + IC(0.180 ns) + CELL(2.700 ns) = 52.420 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'color_interpolation:inst1\|lpm_add_sub:i_rtl_8\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[1\]~130'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "2.880 ns" { color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~132 color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~130 } "NODE_NAME" } } } { "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.180 ns) + CELL(2.700 ns) 55.300 ns color_interpolation:inst1\|lpm_add_sub:i_rtl_8\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\]~128 19 COMB Unassigned 2 " "Info: 19: + IC(0.180 ns) + CELL(2.700 ns) = 55.300 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'color_interpolation:inst1\|lpm_add_sub:i_rtl_8\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\]~128'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "2.880 ns" { color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~130 color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~128 } "NODE_NAME" } } } { "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.180 ns) + CELL(2.700 ns) 58.180 ns color_interpolation:inst1\|lpm_add_sub:i_rtl_8\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~126 20 COMB Unassigned 2 " "Info: 20: + IC(0.180 ns) + CELL(2.700 ns) = 58.180 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'color_interpolation:inst1\|lpm_add_sub:i_rtl_8\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~126'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "2.880 ns" { color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~128 color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~126 } "NODE_NAME" } } } { "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.180 ns) + CELL(2.700 ns) 61.060 ns color_interpolation:inst1\|lpm_add_sub:i_rtl_8\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[4\]~124 21 COMB Unassigned 2 " "Info: 21: + IC(0.180 ns) + CELL(2.700 ns) = 61.060 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'color_interpolation:inst1\|lpm_add_sub:i_rtl_8\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[4\]~124'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "2.880 ns" { color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~126 color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~124 } "NODE_NAME" } } } { "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.180 ns) + CELL(2.700 ns) 63.940 ns color_interpolation:inst1\|lpm_add_sub:i_rtl_8\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[5\]~122 22 COMB Unassigned 2 " "Info: 22: + IC(0.180 ns) + CELL(2.700 ns) = 63.940 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'color_interpolation:inst1\|lpm_add_sub:i_rtl_8\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[5\]~122'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "2.880 ns" { color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~124 color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~122 } "NODE_NAME" } } } { "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.180 ns) + CELL(2.700 ns) 66.820 ns color_interpolation:inst1\|lpm_add_sub:i_rtl_8\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[6\]~120 23 COMB Unassigned 2 " "Info: 23: + IC(0.180 ns) + CELL(2.700 ns) = 66.820 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'color_interpolation:inst1\|lpm_add_sub:i_rtl_8\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[6\]~120'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "2.880 ns" { color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~122 color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~120 } "NODE_NAME" } } } { "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.180 ns) + CELL(2.700 ns) 69.700 ns color_interpolation:inst1\|lpm_add_sub:i_rtl_8\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[7\]~117 24 COMB Unassigned 2 " "Info: 24: + IC(0.180 ns) + CELL(2.700 ns) = 69.700 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'color_interpolation:inst1\|lpm_add_sub:i_rtl_8\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[7\]~117'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "2.880 ns" { color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~120 color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~117 } "NODE_NAME" } } } { "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.180 ns) + CELL(2.700 ns) 72.580 ns color_interpolation:inst1\|lpm_add_sub:i_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[7\]~107 25 COMB Unassigned 2 " "Info: 25: + IC(0.180 ns) + CELL(2.700 ns) = 72.580 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'color_interpolation:inst1\|lpm_add_sub:i_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[7\]~107'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "2.880 ns" { color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~117 color_interpolation:inst1|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~107 } "NODE_NAME" } } } { "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.180 ns) + CELL(2.700 ns) 75.460 ns color_interpolation:inst1\|lpm_add_sub:i_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[8\]~104 26 COMB Unassigned 2 " "Info: 26: + IC(0.180 ns) + CELL(2.700 ns) = 75.460 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'color_interpolation:inst1\|lpm_add_sub:i_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[8\]~104'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "2.880 ns" { color_interpolation:inst1|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~107 color_interpolation:inst1|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~104 } "NODE_NAME" } } } { "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "d:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.180 ns) + CELL(2.700 ns) 78.340 ns color_interpolation:inst1\|i2546~444 27 COMB Unassigned 1 " "Info: 27: + IC(0.180 ns) + CELL(2.700 ns) = 78.340 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'color_interpolation:inst1\|i2546~444'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "2.880 ns" { color_interpolation:inst1|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~104 color_interpolation:inst1|i2546~444 } "NODE_NAME" } } } { "E:/毕业设计/collection/color_interpolation.v" "" "" { Text "E:/毕业设计/collection/color_interpolation.v" 95 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.150 ns) + CELL(2.700 ns) 81.190 ns color_interpolation:inst1\|i2546~445 28 COMB Unassigned 1 " "Info: 28: + IC(0.150 ns) + CELL(2.700 ns) = 81.190 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'color_interpolation:inst1\|i2546~445'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "2.850 ns" { color_interpolation:inst1|i2546~444 color_interpolation:inst1|i2546~445 } "NODE_NAME" } } } { "E:/毕业设计/collection/color_interpolation.v" "" "" { Text "E:/毕业设计/collection/color_interpolation.v" 95 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.150 ns) + CELL(1.700 ns) 83.040 ns color_interpolation:inst1\|Red\[6\]~reg0 29 REG Unassigned 1 " "Info: 29: + IC(0.150 ns) + CELL(1.700 ns) = 83.040 ns; Loc. = Unassigned; Fanout = 1; REG Node = 'color_interpolation:inst1\|Red\[6\]~reg0'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "1.850 ns" { color_interpolation:inst1|i2546~445 color_interpolation:inst1|Red[6]~reg0 } "NODE_NAME" } } } { "E:/毕业设计/collection/color_interpolation.v" "" "" { Text "E:/毕业设计/collection/color_interpolation.v" 114 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "71.700 ns 86.34 % " "Info: Total cell delay = 71.700 ns ( 86.34 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.340 ns 13.66 % " "Info: Total interconnect delay = 11.340 ns ( 13.66 % )" {  } {  } 0}  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "83.040 ns" { collection_buffer:inst|lpm_counter:x_rtl_0|alt_counter_f10ke:wysi_counter|q[3] color_interpolation:inst1|i2216~53 color_interpolation:inst1|i2708~19 color_interpolation:inst1|i8~21 color_interpolation:inst1|i2071~44 color_interpolation:inst1|i2167~49 color_interpolation:inst1|i2159~0 color_interpolation:inst1|i2166~34 color_interpolation:inst1|i~20876 color_interpolation:inst1|i~20877 color_interpolation:inst1|i~20874 color_interpolation:inst1|i~20875 color_interpolation:inst1|i~20264 color_interpolation:inst1|i~20265 color_interpolation:inst1|i~21724 color_interpolation:inst1|i~21758 color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~132 color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~130 color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~128 color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~126 color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~124 color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~122 color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~120 color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~117 color_interpolation:inst1|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~107 color_interpolation:inst1|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~104 color_interpolation:inst1|i2546~444 color_interpolation:inst1|i2546~445 color_interpolation:inst1|Red[6]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iPixClk destination 15.300 ns + Shortest register " "Info: + Shortest clock path from clock iPixClk to destination register is 15.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(10.300 ns) 10.300 ns iPixClk 1 CLK Unassigned 1110 " "Info: 1: + IC(0.000 ns) + CELL(10.300 ns) = 10.300 ns; Loc. = Unassigned; Fanout = 1110; CLK Node = 'iPixClk'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "" { iPixClk } "NODE_NAME" } } } { "E:/verilog/复件 (2) collection/collection.bdf" "" "" { Schematic "E:/verilog/复件 (2) collection/collection.bdf" { { 192 -112 56 208 "iPixClk" "" } { 160 56 56 168 "<<__\$DEF_ALIAS178>>" "" } { 168 56 56 184 "<<__\$DEF_ALIAS50>>" "" } { 184 56 56 200 "<<__\$DEF_ALIAS47>>" "" } { 200 56 56 232 "<<__\$DEF_ALIAS126>>" "" } { 232 56 56 264 "<<__\$DEF_ALIAS139>>" "" } { 144 56 160 160 "<<Link_picture>>" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.000 ns) + CELL(0.000 ns) 15.300 ns color_interpolation:inst1\|Red\[6\]~reg0 2 REG Unassigned 1 " "Info: 2: + IC(5.000 ns) + CELL(0.000 ns) = 15.300 ns; Loc. = Unassigned; Fanout = 1; REG Node = 'color_interpolation:inst1\|Red\[6\]~reg0'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "5.000 ns" { iPixClk color_interpolation:inst1|Red[6]~reg0 } "NODE_NAME" } } } { "E:/毕业设计/collection/color_interpolation.v" "" "" { Text "E:/毕业设计/collection/color_interpolation.v" 114 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.300 ns 67.32 % " "Info: Total cell delay = 10.300 ns ( 67.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.000 ns 32.68 % " "Info: Total interconnect delay = 5.000 ns ( 32.68 % )" {  } {  } 0}  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "15.300 ns" { iPixClk color_interpolation:inst1|Red[6]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iPixClk source 15.300 ns - Longest register " "Info: - Longest clock path from clock iPixClk to source register is 15.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(10.300 ns) 10.300 ns iPixClk 1 CLK Unassigned 1110 " "Info: 1: + IC(0.000 ns) + CELL(10.300 ns) = 10.300 ns; Loc. = Unassigned; Fanout = 1110; CLK Node = 'iPixClk'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "" { iPixClk } "NODE_NAME" } } } { "E:/verilog/复件 (2) collection/collection.bdf" "" "" { Schematic "E:/verilog/复件 (2) collection/collection.bdf" { { 192 -112 56 208 "iPixClk" "" } { 160 56 56 168 "<<__\$DEF_ALIAS178>>" "" } { 168 56 56 184 "<<__\$DEF_ALIAS50>>" "" } { 184 56 56 200 "<<__\$DEF_ALIAS47>>" "" } { 200 56 56 232 "<<__\$DEF_ALIAS126>>" "" } { 232 56 56 264 "<<__\$DEF_ALIAS139>>" "" } { 144 56 160 160 "<<Link_picture>>" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.000 ns) + CELL(0.000 ns) 15.300 ns collection_buffer:inst\|lpm_counter:x_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG Unassigned 103 " "Info: 2: + IC(5.000 ns) + CELL(0.000 ns) = 15.300 ns; Loc. = Unassigned; Fanout = 103; REG Node = 'collection_buffer:inst\|lpm_counter:x_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "5.000 ns" { iPixClk collection_buffer:inst|lpm_counter:x_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } } { "d:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "d:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.300 ns 67.32 % " "Info: Total cell delay = 10.300 ns ( 67.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.000 ns 32.68 % " "Info: Total interconnect delay = 5.000 ns ( 32.68 % )" {  } {  } 0}  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "15.300 ns" { iPixClk collection_buffer:inst|lpm_counter:x_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } }  } 0}  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "15.300 ns" { iPixClk color_interpolation:inst1|Red[6]~reg0 } "NODE_NAME" } } } { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "15.300 ns" { iPixClk collection_buffer:inst|lpm_counter:x_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.400 ns + " "Info: + Micro clock to output delay of source is 1.400 ns" {  } { { "d:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "d:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.600 ns + " "Info: + Micro setup delay of destination is 2.600 ns" {  } { { "E:/毕业设计/collection/color_interpolation.v" "" "" { Text "E:/毕业设计/collection/color_interpolation.v" 114 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "d:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "d:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "E:/毕业设计/collection/color_interpolation.v" "" "" { Text "E:/毕业设计/collection/color_interpolation.v" 114 -1 0 } }  } 0}  } { { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "83.040 ns" { collection_buffer:inst|lpm_counter:x_rtl_0|alt_counter_f10ke:wysi_counter|q[3] color_interpolation:inst1|i2216~53 color_interpolation:inst1|i2708~19 color_interpolation:inst1|i8~21 color_interpolation:inst1|i2071~44 color_interpolation:inst1|i2167~49 color_interpolation:inst1|i2159~0 color_interpolation:inst1|i2166~34 color_interpolation:inst1|i~20876 color_interpolation:inst1|i~20877 color_interpolation:inst1|i~20874 color_interpolation:inst1|i~20875 color_interpolation:inst1|i~20264 color_interpolation:inst1|i~20265 color_interpolation:inst1|i~21724 color_interpolation:inst1|i~21758 color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~132 color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~130 color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~128 color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~126 color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~124 color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~122 color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~120 color_interpolation:inst1|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~117 color_interpolation:inst1|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~107 color_interpolation:inst1|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~104 color_interpolation:inst1|i2546~444 color_interpolation:inst1|i2546~445 color_interpolation:inst1|Red[6]~reg0 } "NODE_NAME" } } } { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "15.300 ns" { iPixClk color_interpolation:inst1|Red[6]~reg0 } "NODE_NAME" } } } { "E:/毕业设计/collection/db/collection_cmp.qrpt" "" "" { Report "E:/毕业设计/collection/db/collection_cmp.qrpt" Compiler "collection" "UNKNOWN" "V1" "E:/毕业设计/collection/db/collection.quartus_db" { Floorplan "" "" "15.300 ns" { iPixClk collection_buffer:inst|lpm_counter:x_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } }  } 0}
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