📄 collection.tan.qmsg
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{ "Warning" "WDAT_POST_SYNTHESIS_TIMING" "" "Warning: Annotating netlist with estimated timing delays -- some delays may be overly pessimistic due to lack of exact fitting information" { } { } 0}
{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "lineValid " "Info: Assuming node lineValid is an undefined clock" { } { { "E:/verilog/复件 (2) collection/collection.bdf" "" "" { Schematic "E:/verilog/复件 (2) collection/collection.bdf" { { 176 -112 56 192 "lineValid" "" } { 160 56 56 168 "<<__\$DEF_ALIAS178>>" "" } { 168 56 56 184 "<<__\$DEF_ALIAS50>>" "" } { 184 56 56 200 "<<__\$DEF_ALIAS47>>" "" } { 200 56 56 232 "<<__\$DEF_ALIAS126>>" "" } { 232 56 56 264 "<<__\$DEF_ALIAS139>>" "" } { 144 56 160 160 "<<Link_picture>>" "" } } } } { "d:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "d:/quartus/bin/Assignment Editor.qase" 1 { { 0 "lineValid" } } } } } 0} { "Info" "ITDB_NODE_MAP_TO_CLK" "iPixClk " "Info: Assuming node iPixClk is an undefined clock" { } { { "E:/verilog/复件 (2) collection/collection.bdf" "" "" { Schematic "E:/verilog/复件 (2) collection/collection.bdf" { { 192 -112 56 208 "iPixClk" "" } { 160 56 56 168 "<<__\$DEF_ALIAS178>>" "" } { 168 56 56 184 "<<__\$DEF_ALIAS50>>" "" } { 184 56 56 200 "<<__\$DEF_ALIAS47>>" "" } { 200 56 56 232 "<<__\$DEF_ALIAS126>>" "" } { 232 56 56 264 "<<__\$DEF_ALIAS139>>" "" } { 144 56 160 160 "<<Link_picture>>" "" } } } } { "d:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "d:/quartus/bin/Assignment Editor.qase" 1 { { 0 "iPixClk" } } } } } 0} { "Info" "ITDB_NODE_MAP_TO_CLK" "frameValid " "Info: Assuming node frameValid is an undefined clock" { } { { "E:/verilog/复件 (2) collection/collection.bdf" "" "" { Schematic "E:/verilog/复件 (2) collection/collection.bdf" { { 160 -112 56 176 "frameValid" "" } { 160 56 56 168 "<<__\$DEF_ALIAS178>>" "" } { 168 56 56 184 "<<__\$DEF_ALIAS50>>" "" } { 184 56 56 200 "<<__\$DEF_ALIAS47>>" "" } { 200 56 56 232 "<<__\$DEF_ALIAS126>>" "" } { 232 56 56 264 "<<__\$DEF_ALIAS139>>" "" } { 144 56 160 160 "<<Link_picture>>" "" } } } } { "d:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "d:/quartus/bin/Assignment Editor.qase" 1 { { 0 "frameValid" } } } } } 0} } { } 0}
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