tx.v

来自「FPGA上实现UART串口原程序」· Verilog 代码 · 共 62 行

module tx(clk,tx,data,txok,txready);
    input clk;
    output tx,txready;
    input[7:0] data;
    input txok;

	 reg tx,txclk;
    reg txready;
	 reg[3:0] bitpos;	 
  	 reg[1:0] state;
	 reg[3:0] cnt;
	 reg[10:0] count;
	 
	 wire[10:0] databuf;
	 parameter idle=1,txrun=2;
  
	 assign databuf={1,1,data,0}; 

   always @(posedge clk)
   begin
    if(count==325) begin
      count<=0;
	   txclk<=1; 
	 end
    else	 begin
      count<=count+1;
	   txclk<=0;
    end 
   end 

  always @(posedge txclk)  //发送
  begin
   case(state)
	idle: begin
	         txready<=1;
	        if(txok==0)  begin
			    cnt<=0;
			    state<=idle;
				 tx<=1;	   end
			   else   begin 
				  state<=txrun;
				  bitpos<=0; end
          end
   txrun: begin  	
				  txready<=0;
			  if(cnt==15) begin
			    cnt<=0;
	          tx<=databuf[bitpos];
			    bitpos<=bitpos+1;
			    if(bitpos==10)  begin
			      bitpos<=0;
				   state<=idle;
             end
           end
			  else  cnt<=cnt+1;
			  end
    default: state<=idle;
    endcase
   end    
    
endmodule