baudselect.v

来自「FPGA上实现UART串口原程序」· Verilog 代码 · 共 53 行

module baudselect(baud,clk,key);
    input clk;
    output [13:0] baud;
    input key;


	 reg [13:0] baud;
	 reg[13:0] count;
	 reg scan;
	 reg[9:0] keyshift;
	 reg[3:0] select;



always @(posedge clk)
begin
 if(count==5000) begin
   count<=0;
	scan<=1;
 end
 else  begin
  count<=count+1;
  scan<=0;
  end
end

always @(posedge scan)
begin
 keyshift<={keyshift[8:0],key};
 if(keyshift==512) begin
  if(select<4)
    select<=select+1;
	 else
	 select<=0;
 end  
 end
 

always @(posedge clk)
begin
 case(select)
 1: baud=10416;
 2: baud=325;	//9600
 3: baud=162;
 4: baud=26;
 default: baud=325;
 endcase
end



endmodule