uart.npl

FPGA上实现UART串口原程序

JDF G
// Created by Project Navigator ver 1.0
PROJECT uart
DESIGN uart
DEVFAM spartan3
DEVFAMTIME 0
DEVICE xc3s200
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -4
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL Verilog
GENERATEDSIMULATIONMODELTIME 1118886587
DOCUMENT 说明
SOURCE rx.v
SOURCE top.v
SOURCE txdata.v
SOURCE key.v
SOURCE tx.v
DEPASSOC top top.ucf
[STRATEGY-LIST]
Normal=True