key.v

来自「FPGA上实现UART串口原程序」· Verilog 代码 · 共 48 行

//*************************************//
//          按键检测    V 0.1				//
//                      BooQuai        //
//			2005-6-16							//
//     10K时钟扫描 ,  10位 SR 消抖     //
//     检测按键后 发出取值信号wr			//
//*************************************//

module key(clk,key,wr,select);
input clk,key;
output wr;
output[7:0] select;

reg wr;
reg [14:0] count;
reg scan;
reg[9:0]	keyshift;
reg[7:0] select;

always @(posedge clk)		 //10000Hz
begin
 if(count==5000) begin
   count<=0;
	scan<=1;
 end
 else  begin
  count<=count+1;
  scan<=0;
  end
end

always @(posedge scan)
begin
 keyshift<={keyshift[8:0],key};  //移位寄存
 if(keyshift==512)					//判断按键
  begin
   //wr<=0;
  if(select==15)						//按键处理，按需要处理
    select<=0;
	 else
	 select<=select+1;   
  end  
 else wr<=1;
end
 

endmodule