📄 philips_dtv_ref3.h
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/*
* Copyright (c) 1995,1996,1997 by TriMedia Technologies.
*
* +------------------------------------------------------------------+
* | This software is furnished under a license and may only be used |
* | and copied in accordance with the terms and conditions of such |
* | a license and with the inclusion of this copyright notice. This |
* | software or any other copies of this software may not be provided|
* | or otherwise made available to any other person. The ownership |
* | and title of this software is not transferred. |
* | |
* | The information in this software is subject to change without |
* | any prior notice and should not be construed as a commitment by |
* | TriMedia Technologies. |
* | |
* | this code and information is provided "as is" without any |
* | warranty of any kind, either expressed or implied, including but |
* | not limited to the implied warranties of merchantability and/or |
* | fitness for any particular purpose. |
* +------------------------------------------------------------------+
*
* Module name : philips_dtv_ref3.h 1.4
*
* Last update : 18:59:27 - 00/11/09
*
* Description :
*
* Board Support Package for Trimedia peripherals.
* This particular file supports the Philips DTV Board.
* The purpose of this file is to define philips_dtv_ref3_config.
* This board config structure will be included in a table
* in boardcfg.c
*
* Revision :
*
*
*
*/
#include <tm1/tmBoard.h>
#ifndef _PHILIPS_DTV_REF3_H_
#define _PHILIPS_DTV_REF3_H_
#define IIC_EXPANDER_ADDRESS (0x70)
#define L3_IIC_EXPANDER_ADDRESS (0x74)
#define AUDIO_MASTER_IIC_ADDRESS (0x7A)
#define REF3_ISA_BASE_ADDRESS (0x100)
#define FPGA_AUDIO_REG_ADDRESS (REF3_ISA_BASE_ADDRESS + 4)
#define ISA_ADDRESS_MEM_CTL_WR (REF3_ISA_BASE_ADDRESS + 0x10)
/********************** IIC ADDRESS MAP **********************************/
/* IIC_EXPANDER_ADDRESS
address 0x70 : MODE_CONTROL
bit 0 SRESET : Software reset control
bit 1 Afe reset : Modem reset control
bit 2 Rec Select : Selects between TS/ VO signals
bit 3 Play OE# : Enables data flow from/to 1394
bit 4 RTC_SEL : Toggle between BOOT EEPROM/RTC
bit 5 unused
bit 6 unused
bit 7 PARA_SEL : Select ISA parallel port
Detail description:
Play_OE Rec Select
0 0 : AVData -> TS_Data; VICLK -> AVCLK;
AVVALID -> VI_VAL; AVSYNCOUT -> VI_DATA8
0 1 : AVData -> VO_DATA; VICLK -> AVCLK;
AVVALID -> VI_VAL; AVSYNCOUT -> VI_DATA8
1 0 : TS_DATA -> AVData; TS_CLK -> AVCLK;
TS_VAL -> AVVALID; TS_SOP ->AVSYNC
1 1 : VO_DATA -> AVData; VO_CLK -> AVCLK;
VO_IO1 -> AVVALID; VO_IO2 ->AVSYNC
*/
#define IIC_MODE_SRESET (0x01)
#define IIC_MODE_AFE_RESET (0x02)
#define IIC_MODE_REC_SEL (0x04)
#define IIC_MODE_PLAY (0x08)
#define IIC_MODE_RTC_SEL (0x10)
#define IIC_MODE_PARA_SEL (0x80)
/* L3_IIC_EXPANDER_ADDRESS
address 0x74 : L3_OUTPUT_CONTROL
bit 0 Dout L3 mode
bit 1 Dout L3 clock
bit 2 Dout L3 data
bit 3 Dout L3 strobe
bit 4 Mute SPDIF TX
bit 5 AOSD GATE
bit 6 unused
bit 7 unused
*/
#define REF3_OUTPUT_L3_MODE (0x01)
#define REF3_OUTPUT_L3_CLOCK (0x02)
#define REF3_OUTPUT_L3_DATA (0x04)
#define REF3_OUTPUT_L3_STROBE (0x08)
#define REF3_OUTPUT_L3_MUTE_SPDIF (0x10)
#define REF3_OUTPUT_L3_AOSD_GATE (0x20)
/* AUDIO_MASTER_IIC_ADDRESS
address: 0x7A Audio master control
bit 0 ACS0_M
bit 1 ACS0_DATA
bit 2 ACS1_M
bit 3 ACS1_DATA
bit 4 MUTE
bit 5 DEMP
bit 6 PWRDWN
bit 7 unused
*/
#define ACS0_M_BIT (0x01)
#define ACS0_DATA_BIT (0x02)
#define ACS1_M_BIT (0x04)
#define ACS1_DATA_BIT (0x08)
#define SPDIF_MUTE (0x10)
#define SPDIF_DEMP (0x20)
#define SPDIF_PWRDWN (0x40)
/********************** ISA ADDRESS MEMORY MAP **********************************/
/* ISA_FPGA Interface Base address 0x100 */
#define TOTAL_NO_OF_FPGA_REGS 8
#define FPGA_REG0 0
#define FPGA_REG1 1
#define FPGA_REG2 2
#define FPGA_REG3 3
#define FPGA_REG4 4
#define FPGA_REG5 5
#define FPGA_REG6 6
#define FPGA_REG7 7
/*
ISA address 0x100 : FPGA_REG0 Chrontel CH8439 YUV to RGB DAC interface
(Write Only)
bit 0 unused
bit 1 unused
bit 2 unused
bit 3 ALIS_CS
bit 4 CH_CLK
bit 5 CH_WR_DATA
bit 6 CH_CS
bit 7 GEN_CS
*/
#define FPGA_REG0_ALIS_CS (0x08)
#define FPGA_REG0_CH_CLK (0x10)
#define FPGA_REG0_CH_WR_DATA (0x20)
#define FPGA_REG0_CH_CS (0x40)
#define FPGA_REG0_GEN_CS (0x80)
/*
ISA address 0x101 : FPGA_REG1 reserved
*/
/*
ISA address 0x102 : FPGA_REG2 INTERRUPT_STATUS (Read Only)
bit 0 L3_INT_STATUS : 1 = L3 interrupt from Status
bit 1 L3_INT_CONTROL : 1 = L3 interrupt from Control
bit 2 INT_RC5 : It is clear on reading this bit.
bit 3 unused
bit 4 unused
bit 5 CH_RD_DATA
bit 6 unused
bit 7 unused
*/
#define FPGA_REG2_L3_INT_STATUS (0x01)
#define FPGA_REG2_L3_INT_CONTROL (0x02)
#define FPGA_REG2_INT_RC5 (0x04)
#define FPGA_REG2_CH_RD_DATA (0x20)
/*
ISA address 0x103 : FPGA_REG3 VIDEO_L3_MODE (Write Only)
bit 0 Vmode bit0 : Vmode [0:3] : 0 = HD_DECODE;
bit 1 Vmode bit1 1 = SD_DECODE;
bit 2 Vmode bit2 2 = TM_MASTER;
bit 3 Vmode bit3 3 = TM_SD_DECODE;
bit 4 Lmode bit0 : Lmode [0:3] : 0 = IDLE; 1 = FPGA_L3_MASTER;
bit 5 Lmode bit1 2 = FPGA_L3_CONTROL; 3 = READ_SPDIF_LSB
bit 6 Lmode bit2 4 = READ_SPDIF_MSB
bit 7 Lmode bit3
*/
#define FPGA_REG3_VMODE_MASK (0x0F)
#define FPGA_REG3_VMODE_HD_DECODE (0x00)
#define FPGA_REG3_VMODE_SD_DECODE (0x01)
#define FPGA_REG3_VMODE_TM_MASTER (0x02)
#define FPGA_REG3_VMODE_TM_SD_DECODE (0x03)
#define FPGA_REG3_LMODE_MASK (0xF0)
/*
ISA address 0x104 : FPGA_REG4 AUDIO_MODE (Write only)
bit 0 AudioCh 0 : AudioCh[0:1] 0 = 2 ch, 1 = 4 ch,
bit 1 AudioCh 1 2 = 6 ch, 3 = 8 ch
bit 2 AudioData 1 = 16bit, 0= 32bit(20bit)
bit 3 Mute 0 = Mute, 1= unmute
bit 4 AudioReset 0 = reset, 1= unreset
bit 5 unused
bit 6 unused
bit 7 unused
*/
#define FPGA_REG4_AUDIO_CH_MASK (0x03)
#define FPGA_REG4_AUDIO_2CH (0x00)
#define FPGA_REG4_AUDIO_4CH (0x01)
#define FPGA_REG4_AUDIO_6CH (0x02)
#define FPGA_REG4_AUDIO_8CH (0x03)
#define FPGA_REG4_AUDIO_DATA (0x04)
#define FPGA_REG4_AUDIO_MUTE (0x08)
#define FPGA_REG4_AUDIO_RESET (0x10)
/*
ISA address 0x105 : FPGA_REG5 SPDIF RD LSB Byte
*/
/*
ISA address 0x106 : FPGA_REG6 SPDIF RD MSB Byte
*/
/*
ISA address 0x107 : FPGA_REG7 INTERRUPT_STATUS (Read Only)
bit 0 unused
bit 1 PCMCIA_INT
bit 2 COM_A_INT
bit 3 MICRO_INT
bit 4 RTC_INT
bit 5 AVL_INT
bit 6 SOUTH_BRIDGE_INT
bit 7 MODEM_INT
*/
#define FPGA_REG7_PCMCIA_INT (0x02)
#define FPGA_REG7_COM_A_INT (0x04)
#define FPGA_REG7_MICRO_INT (0x08)
#define FPGA_REG7_RTC_INT (0x10)
#define FPGA_REG7_AVL_INT (0x20)
#define FPGA_REG7_SOUTH_INT (0x40)
#define FPGA_REG7_MODEM_INT (0x80)
/*
ISA ADDRESS 0x110 : MEM_CTL_WR Register (Write only)
bit 0 PAGE 0
bit 1 PAGE 1
bit 2 RTC_RESET
bit 3 RTS_FLASH
bit 4 CLK_MUX
bit 5 unused
bit 6 unused
bit 7 unused
*/
#define MEM_CTL_WR_FLASH_MASK (0x03)
#define MEM_CTL_WR_FLASH_PAGE0 (0x01)
#define MEM_CTL_WR_FLASH_PAGE1 (0x02)
#define MEM_CTL_WR_RTC_RESET (0x04)
#define MEM_CTL_WR_RTS_FLASH (0x08)
#define MEM_CTL_WR_CLK_MUX (0x10)
/*
ISA ADDRESS 0x111 : MEM_CTL_RD Register (Read only)
bit 0 : MEMSIZE 0 = 1Mx8, 1= 2Mx8 Flash memory
bit 1:7 : unused
*/
#define MEM_CTL_RD_MEMSIZE (0x01)
/********************** ISA ADDRESS IO MAP DEVICES **********************************/
/************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
extern boardConfig_t philips_dtv_ref3_config;
#if defined(__cplusplus)
}
#endif
#endif /* _PHILIPS_DTV_REF3_H_ */
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