dtv_ref3_video.c

用于TM1300/PNX1300系列DSP（主要用于视频处理）的设备库的源码

/*
 * Copyright (c) 1995,1996,1997 by TriMedia Technologies. 
 *
 * +------------------------------------------------------------------+
 * | This software is furnished under a license and may only be used  |
 * | and copied in accordance with the terms and conditions of  such  |
 * | a license and with the inclusion of this copyright notice. This  |
 * | software or any other copies of this software may not be provided|
 * | or otherwise made available to any other person.  The ownership  |
 * | and title of this software is not transferred.                   |
 * |                                                                  |
 * | The information in this software is subject  to change without   |
 * | any  prior notice and should not be construed as a commitment by |
 * | TriMedia Technologies.                                           |
 * |                                                                  |
 * | this code and information is provided "as is" without any        |
 * | warranty of any kind, either expressed or implied, including but |
 * | not limited to the implied warranties of merchantability and/or  |
 * | fitness for any particular purpose.                              |
 * +------------------------------------------------------------------+
 *
 *  Module name              : dtv_ref3_video.c    1.11
 *
 *  Last update              : 18:59:26 - 00/11/09
 *
 *  Description              :
 *
 *
 */

#include <tm1/tmAvFormats.h>
#include <tm1/tmLibdevErr.h>
#include <tm1/tmProcessor.h>
#include "philips_dtv_ref3.h"
#include "dtv_ref3_video.h"
#include "saa7125.h"
#include <tm1/tmVOmmio.h>
#include "ref3_prphr.h"

static tmVideoAnalogStandard_t dtv_vo_standard;

/********************* Ref3 Video Control Driver *************************/
static tmLibdevErr_t _dtv_ref3_VO_Mode(UInt8 VMode)
{
    /* Enable proper Clk mux */
    if((VMode == FPGA_REG3_VMODE_TM_MASTER) ||
       (VMode == FPGA_REG3_VMODE_TM_SD_DECODE))
    {
       /* Trimedia as vo clock master */
       IsaMemCtlWrite(MEM_CTL_WR_CLK_MUX, MEM_CTL_WR_CLK_MUX);
    }
    else
    {
       /* st7000 as vo clock master */
       IsaMemCtlWrite(MEM_CTL_WR_CLK_MUX, ~MEM_CTL_WR_CLK_MUX);
    }
    FpgaWriteReg( FPGA_REG3, FPGA_REG3_VMODE_MASK, VMode);
    return TMLIBDEV_OK;
}

tmLibdevErr_t 
dtv_ref3_VO_Init(pboardVOParam_t param)
{
    tmLibdevErr_t rval = TMLIBDEV_OK;
    pprocCapabilities_t procCap;

    rval = procGetCapabilities(&procCap);
    if (rval) return rval;

    switch ( param->videoStandard)
    {
    case vasNTSC :
    case vasPAL  :
        _dtv_ref3_VO_Mode(FPGA_REG3_VMODE_TM_SD_DECODE);
        rval = saa7125Init(param);
        if (rval) return rval;
        /* There is a bug in the GOMAD board, bug 502807, here is the workaround */
        rval = saa7125Configure(0x6c, 0x2d);	/* set h trigger to start of pixel */
        rval = saa7125Configure(0x6d, 0x3f);	/* set h trigger to start of line */
        break;
     
    case vas768x576p:
    case vas720x480p :
        if (dtv_vo_standard & SAA7125_SUPPORTED_STANDARDS)
            dtv_ref3_VO_Stop();
        _dtv_ref3_VO_Mode(FPGA_REG3_VMODE_TM_MASTER);
        break;

    case vas960x540p : /* TM is VO slave */ 
        if (dtv_vo_standard & SAA7125_SUPPORTED_STANDARDS)
            dtv_ref3_VO_Stop();

        _dtv_ref3_VO_Mode(FPGA_REG3_VMODE_HD_DECODE);
        break;

    default :
        rval = VO_ERR_STANDARD_NOT_SUPPORTED;
    }
    dtv_vo_standard = param->videoStandard;
    
    voSetFREQUENCY__CHECK(param->ddsFrequency);
    voSetPLL_S__CHECK(1);
    voSetPLL_T__CHECK(1);
    voSetCLKOUT__CHECK(1);
    voSetSYNC_MASTER__CHECK(1);

    switch (param->videoStandard)
    {
    case vasNTSC:
        voSupportNTSC();
        break;
    case vasPAL:
        voSupportPAL();
        break;
    case vas720x480p: /* NTSC progressive */
        voSetPLL_T__CHECK(3);   /* this double the VO CLK; freq 54 MHz */
        voSupport720x480p();
        break;
    case vas768x576p: /* PAL progressive */
        voSetPLL_T__CHECK(3);   /* this double the VO CLK; freq 54 MHz */
        voSupport768x576p();
        break;
    case vas960x540p: /* 1080i overlay for DTV */
        voSetCLKOUT__CHECK(0);
        voSetSYNC_MASTER__CHECK(0);
        voSetIO1_POS__CHECK(1);
        voSetIO2_POS__CHECK(1);

        /* TM1100 specific code (ifdef tm1100 removed) */
        if (procCap->deviceID != PROC_DEVICE_TM1000)
        {
            MMIO(EVO_SLVDLY) = 2200 - 10; /* genlock delay  */
	    MMIO(EVO_CTL) = 0x10000041; /* genlock enable */
        }
        voSupport960x540p();
        break;
    }
    return (rval);
}

/**   Public Config function ****/
tmLibdevErr_t 
dtv_ref3_VO_Configure(UInt32 subaddr, UInt32 value)
{
    tmLibdevErr_t rval = TMLIBDEV_OK;

    if( dtv_vo_standard & SAA7125_SUPPORTED_STANDARDS )
    {
        rval = saa7125Configure( subaddr, value);
    } 
    return (rval);
}

tmLibdevErr_t 
dtv_ref3_VO_Stop()
{
    tmLibdevErr_t rval = TMLIBDEV_OK;
    
    if( dtv_vo_standard & SAA7125_SUPPORTED_STANDARDS )
    {
        rval = saa7125Stop( dtv_vo_standard );
    } 
    return (rval);
}

tmLibdevErr_t 
dtv_ref3_VO_SetBrightness(UInt val)
{
    tmLibdevErr_t rval = TMLIBDEV_OK;
    
    if( dtv_vo_standard & SAA7125_SUPPORTED_STANDARDS )
    {
        rval = saa7125SetBrightness( val);
    } 
    return (rval);
}