ref3_prphr.c

用于TM1300/PNX1300系列DSP（主要用于视频处理）的设备库的源码

/*
 * Copyright (c) 1995,1996,1997 by TriMedia Technologies. 
 *
 * +------------------------------------------------------------------+
 * | This software is furnished under a license and may only be used  |
 * | and copied in accordance with the terms and conditions of  such  |
 * | a license and with the inclusion of this copyright notice. This  |
 * | software or any other copies of this software may not be provided|
 * | or otherwise made available to any other person.  The ownership  |
 * | and title of this software is not transferred.                   |
 * |                                                                  |
 * | The information in this software is subject  to change without   |
 * | any  prior notice and should not be construed as a commitment by |
 * | TriMedia Technologies.                                           |
 * |                                                                  |
 * | this code and information is provided "as is" without any        |
 * | warranty of any kind, either expressed or implied, including but |
 * | not limited to the implied warranties of merchantability and/or  |
 * | fitness for any particular purpose.                              |
 * +------------------------------------------------------------------+
 *
 *  Module name              : ref3_prphr.c    1.7
 *
 *  Last update              : 18:59:27 - 00/11/09
 *
 *  Description              :
 *
 * Drivers for Dtv Ref3 (GOMAD) peripherals. This particular file supports
 * PCI, WinBond PIC. Defines Generic Interrupt C handler.
 *
 * Revision                 :
 *
 *
 */

/* --------------------------- includes ----------------------------------- */

#include <stdio.h>
#include <tmlib/tmtypes.h>
#include <tm1/mmio.h>
#include <tm1/tmBoard.h>
#include <tm1/tmPCI.h>
#include <tm1/tmLibdevErr.h>
#include <tm1/tmInterrupts.h>
#include <tmlib/dprintf.h>
#include <tmlib/AppModel.h>
#include "philips_dtv_ref3.h"
#include "ref3_prphr.h" /* global definitions */
#include "ref3_prphr_int.h" /* local definitions */

/*************************** Chrontel Driver *******************************/

#define CH_LATCH_WR (REF3_ISA_BASE_ADDRESS + FPGA_REG0)

#define DELAY_TIME 0x08

static UInt8 ChLatch = FPGA_REG0_CH_WR_DATA|FPGA_REG0_CH_CLK;

static void ChrontelAccess( void )
{
    UInt8 Delay; 
    for(Delay = 0; Delay < DELAY_TIME;Delay++)
    pciMemoryWriteUInt8((UInt8*)CH_LATCH_WR,ChLatch);
}
static void ChrontelWrite(UInt8 Addr, UInt8 Data)
{
    UInt8 TempByte,i;

    /* Make CS = 1 */
    ChLatch |= FPGA_REG0_CH_CS;
    ChrontelAccess();

    /* Generate Start Condition CS_DATA going low when clock high */
    ChLatch &= ~(FPGA_REG0_CH_WR_DATA);
    ChrontelAccess();

    /* Pull clock low */
    ChLatch &= ~(FPGA_REG0_CH_CLK);
    ChrontelAccess();

    /* Send Read/ Write Bit ( always write ;)  */
    ChLatch &= ~(FPGA_REG0_CH_WR_DATA);
    ChrontelAccess();
    ChLatch |= FPGA_REG0_CH_CLK;
    ChrontelAccess();

    /* Send AutoInc Bit = 0 (Data already 0 just clock) */
    ChLatch &= ~(FPGA_REG0_CH_CLK);
    ChrontelAccess();
    ChLatch |= FPGA_REG0_CH_CLK;
    ChrontelAccess();

    /* Send undefined bit as 0 ( Data already 0 just clock ) */
    ChLatch &= ~(FPGA_REG0_CH_CLK);
    ChrontelAccess();

    ChLatch |= FPGA_REG0_CH_CLK;
    ChrontelAccess();

    /* Send five Address Bits */
    for( i=0;i<5;i++)
    {
        TempByte = ((Addr>>(4-i))&0x01)<<5;
        ChLatch &= ~(FPGA_REG0_CH_CLK);
        ChrontelAccess();

        ChLatch &= ~(FPGA_REG0_CH_WR_DATA);
        ChLatch |= TempByte;
        ChrontelAccess();

        ChLatch |= FPGA_REG0_CH_CLK;
        ChrontelAccess();    
    };
    /* Send Low during Ack Bit */
    ChLatch &= ~(FPGA_REG0_CH_CLK);
    ChrontelAccess();    

    ChLatch &= ~(FPGA_REG0_CH_WR_DATA);
    ChrontelAccess();    

    ChLatch |= FPGA_REG0_CH_CLK;
    ChrontelAccess();    

    /* Send Eight Data Bits */
    for( i=0;i<8;i++)
    {
        TempByte = ((Data>>(7-i))&0x01)<<5;
        ChLatch &= ~(FPGA_REG0_CH_CLK);
        ChrontelAccess();    

        ChLatch &= ~(FPGA_REG0_CH_WR_DATA);
        ChLatch |= TempByte;
        ChrontelAccess();    

        ChLatch |= FPGA_REG0_CH_CLK;
        ChrontelAccess();    
    };
    /* Send Low during Ack Bit */
    ChLatch &= ~(FPGA_REG0_CH_CLK);
    ChrontelAccess();    
    ChLatch &= ~(FPGA_REG0_CH_WR_DATA);
    ChrontelAccess();    
    ChLatch |= FPGA_REG0_CH_CLK;
    ChrontelAccess();    
    ChLatch &= ~(FPGA_REG0_CH_CLK);
    ChrontelAccess();    
    /* generate Stop condition Pull Clock up then pull data high with clock hi */

    ChLatch |= FPGA_REG0_CH_CLK;
    ChrontelAccess();    
    ChLatch |= FPGA_REG0_CH_WR_DATA;
    ChrontelAccess();    

    /* Take out CS */
    ChLatch &= ~(FPGA_REG0_CH_CS);     /* Give twice delay */
    ChrontelAccess();    
    ChrontelAccess();    
}


 /* Chrontel initialisation */
static void ChrontelInit(void)
{
    ChrontelWrite( 4, 0xF);
    ChrontelWrite( 5, 0xF);
    ChrontelWrite( 6, 0xF);
 
    ChrontelWrite( 7, 0x07);
    ChrontelWrite( 8, 0x40);
    ChrontelWrite( 9, 0x07);
    ChrontelWrite( 10, 0x40);
    ChrontelWrite( 11, 0x07);
    ChrontelWrite( 12, 0x40);
 
    ChrontelWrite( 16, 0xB0);
    ChrontelWrite( 0, 5);
}

/********************* FPGA Driver *********************************/

static UInt8 FpgaReg[TOTAL_NO_OF_FPGA_REGS];

extern void FpgaWriteReg(UInt8 Register, UInt8 FieldMask, UInt8 Data)
{
   if (Register < TOTAL_NO_OF_FPGA_REGS	)
   {
      FpgaReg[Register] &= ~FieldMask;
      FpgaReg[Register] |= (Data & FieldMask);
      pciMemoryWriteUInt8((UInt8*)REF3_ISA_BASE_ADDRESS + Register,FpgaReg[Register]);
   }
   
}

extern UInt8 FpgaReadReg(UInt8 Register)
{
   if (Register < TOTAL_NO_OF_FPGA_REGS	)
   {
      return(*(UInt8 *)(REF3_ISA_BASE_ADDRESS + Register));
   }
   return 0;
}

/********************* ISA MEM CTL  Driver *********************************/
static UInt8 IsaMemCtlReg = 0;

extern void IsaMemCtlWrite(UInt8 FieldMask, UInt8 Data)
{
      IsaMemCtlReg &= ~FieldMask;
      IsaMemCtlReg |= (Data & FieldMask);
      pciMemoryWriteUInt8((UInt8*)ISA_ADDRESS_MEM_CTL_WR, IsaMemCtlReg);
}

/********************* Peripheral Init *********************************/
/* Peripheral init is called in dtv_ref3_board_init() */
extern void ref3_prphr_init(void)
{
    ChrontelInit();
}