📄 philips_dtv_ref3.c
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irqNum = ref3IrqArray[source];
if(irqNum < 8)
{
ref3PicMasterMask &= (~( 0x01 << irqNum ));
err = pciIOWriteUInt8(M_OCW1,ref3PicMasterMask);
if (err)
return err;
}
else
{
ref3PicSlaveMask &= (~( 0x01 << (irqNum-8) ));
err = pciIOWriteUInt8(S_OCW1,ref3PicSlaveMask);
if (err)
return err;
}
return TMLIBDEV_OK;
}
static Bool dtvRef3PICSourceDetect(UInt32 * source)
{
UInt8 irqNum = 0xff;
UInt32 data;
tmLibdevErr_t err;
Bool retVal;
err = pciIOWriteUInt8(M_OCW3,POLL_CMD);
if (err)
DP((" Error in dtvRef3PICSourceDetect: %#x\n", err));
err = pciIOReadUInt8(M_OCW3, &data);
if (err)
DP((" Error in dtvRef3PICSourceDetect: %#x\n", err));
if(data & 0x80)
{
irqNum = data & 0x07;
if(irqNum == 0x02)
{
err = pciIOWriteUInt8(S_OCW3,POLL_CMD);
if (err)
DP((" Error in dtvRef3PICSourceDetect: %#x\n", err));
err = pciIOReadUInt8(S_OCW3, &data);
if (err)
DP((" Error in dtvRef3PICSourceDetect: %#x\n", err));
if(data & 0x80)
{
irqNum = (data & 0x07) + 8;
}
else
{
irqNum = 0xff;
}
}
}
retVal = (irqNum != 0xff)?True : False;
*source = (irqNum != 0xff)?ref3Irq2SrcArray[irqNum] : 0xff;
return retVal;
}
static tmLibdevErr_t dtvRef3PICTerm(UInt32 source)
{
UInt8 irqNum;
tmLibdevErr_t err;
if (source >= DTV_REF3_PIC_NUM_SRCS)
return PIC_ERR_SOURCE_NOT_AVAILABLE;
irqNum = ref3IrqArray[source];
if(irqNum < 8)
{
ref3PicMasterMask |= (0x01 << irqNum);
err = pciIOWriteUInt8(M_OCW1,ref3PicMasterMask);
if (err)
return err;
}
else
{
ref3PicSlaveMask |= (0x01 << (irqNum-8));
err = pciIOWriteUInt8(S_OCW1,ref3PicSlaveMask);
if (err)
return err;
}
return TMLIBDEV_OK;
}
static tmLibdevErr_t dtvRef3PICStart(UInt32 source)
{
return TMLIBDEV_OK;
}
static tmLibdevErr_t dtvRef3PICStop(UInt32 source)
{
return TMLIBDEV_OK;
}
static tmLibdevErr_t dtvRef3PICAck(UInt32 source)
{
UInt8 irqNum = 0xff;
tmLibdevErr_t err;
if (source >= DTV_REF3_PIC_NUM_SRCS)
return PIC_ERR_SOURCE_NOT_AVAILABLE;
irqNum = ref3IrqArray[source];
if (irqNum > 7)
{
err = pciIOWriteUInt8(S_OCW2,EOI_CMD);
if (err)
DP((" Error in dtvRef3PICAck: %#x\n", err));
}
err = pciIOWriteUInt8(M_OCW2,EOI_CMD);
if (err)
DP((" Error in dtvRef3PICAck: %#x\n", err));
return TMLIBDEV_OK;
}
/******************************* IR functions **************************************/
static tmLibdevErr_t dtvRef3IRInit(pboardIRParam_t params)
{
tmLibdevErr_t err;
w83977atfIRParams_t sioIrParams;
sioIrParams.irDevice = params->device;
err = w83977atfIRInit(&sioIrParams);
return err;
}
static tmLibdevErr_t dtvRef3IRTerm(void)
{
return TMLIBDEV_OK;
}
static tmLibdevErr_t dtvRef3IRStart(void)
{
return TMLIBDEV_OK;
}
static tmLibdevErr_t dtvRef3IRStop(void)
{
return TMLIBDEV_OK;
}
static void dtvRef3IRGetEvent(tsaIREvent_t *event, UInt32 *value)
{
w83977atfIRGetEvent(event, value);
}
/******************************* board functions **************************************/
static tmLibdevErr_t dtv_ref3_board_activate(pcomponent_t comp)
{
Int32 err;
L1_DP(("dtv_ref3_board_activate\n"));
err = dtv_ref3_board_detect();
if (err != TMLIBDEV_OK)
{
L2_DP(("Board not recognized\n"));
return err;
}
L2_DP(("Board recognized\n"));
TRY(dtv_ref3_board_init());
/* the board has to be registered now */
TRY(dtv_ref3_board_register(comp));
return TMLIBDEV_OK;
}
/******************** dtv_board_init *******************************
* The dtv board comes up with peripherals reset.
* This function takes the board out of reset and leaves
* it in a good state.
*/
static tmLibdevErr_t
dtv_ref3_board_init(void)
{
Int32 iicd;
pprocCapabilities_t procCap;
UInt32 southAddr;
UInt32 tmAddr;
w83977atfParams_t sioParams;
TRY(procGetCapabilities(&procCap));
MMIO(SSI_CTL) = 0x00040000; /* V34IO2 goes high to stay on hook! */
/* Initialize PCI space */
TRY(pciAddressFind(PCI_VENDOR_ID_TM1S_IREF, &tmAddr));
TRY(pciAddressFind(PCI_VENDOR_ID_SOUTH, &southAddr));
TRY(pciConfigWrite((southAddr | 0x04), 0x00000007));
TRY(pciConfigWrite((southAddr | 0x0c), 0x0000FF10));
TRY(pciConfigWrite((southAddr | 0x3C), 0x00000107));
TRY(pciConfigWrite((southAddr | 0x4C), 0x00041000));
/* Set Trimedia as vo clock master and generate VO clock so that SAA7125
does not affect IIC transfers */
IsaMemCtlWrite(MEM_CTL_WR_CLK_MUX, MEM_CTL_WR_CLK_MUX);
MMIO(VO_CLOCK) = (UInt) (0.5 + (1431655765.0 * VO_FREQUENCY / (Float) procCap->cpuClockFrequency));
MMIO(VO_CTL) = 0x02700000;
/* Does software reset to the board */
iicd = 0xFF;
iicd &= ~IIC_MODE_SRESET;
TRY(iicWriteReg(IIC_EXPANDER_ADDRESS, -1, iicd)); /* lower reset */
iicd |= IIC_MODE_SRESET; /* set SRESET bit; raise reset */
iicd &= ~IIC_MODE_REC_SEL; /* select TS data and control signals */
iicd |= IIC_MODE_PLAY; /* disable Play mode */
TRY(iicWriteReg(IIC_EXPANDER_ADDRESS, -1, iicd));
/* set L3_OUTPUT_CONTOL to default state */
TRY(iicWriteReg(L3_IIC_EXPANDER_ADDRESS, -1, 0xFF));
/* initialize peripherals */
ref3_prphr_init();
/* initialize PICs */
/* Init the Master and slave 8259 with all IRQs masked */
TRY(pciIOWriteUInt8(M_ICW1,ICW1_VAL));
TRY(pciIOWriteUInt8(M_ICW2,M_ICW2_VAL));
TRY(pciIOWriteUInt8(M_ICW3,M_ICW3_VAL));
TRY(pciIOWriteUInt8(M_ICW4,ICW4_VAL));
TRY(pciIOWriteUInt8(S_ICW1,ICW1_VAL));
TRY(pciIOWriteUInt8(S_ICW2,S_ICW2_VAL));
TRY(pciIOWriteUInt8(S_ICW3,S_ICW3_VAL));
TRY(pciIOWriteUInt8(S_ICW4,ICW4_VAL));
/* MASK OFF all IRQs except IRQ2 in master since this is used for cascade */
ref3PicMasterMask = M_OCW1_VAL;
ref3PicSlaveMask = S_OCW1_VAL;
pciIOWriteUInt8(M_OCW1,ref3PicMasterMask);
pciIOWriteUInt8(S_OCW1,ref3PicSlaveMask);
/* enable PIC int on FPGA */
pciMemoryWriteUInt8((UInt8*)FPGA_INT_ENABLE_REG, 0x40);
/* initialize super I/O */
sioParams.sioWriteFunc = ref3SioWrite;
sioParams.sioReadFunc = pciIOReadUInt8;
sioParams.sharedInterrupts = False;
TRY(w83977atfInit(&sioParams));
/* Don't want TriMedia to drive VO clock and sync since st7000
* is also doing it. Without this, we have lift 3 pins on TriMedia
* in the DTV reference board 1 and C1_1 board
*/
MMIO(VO_CTL) = 0x32400000; /* The hardware default value after reset */
MMIO(VO_CLOCK) = 0; /* reset VO clock */
/* if we get there, everything went all right */
return TMLIBDEV_OK;
} /* end of dtv_board_init() */
/******************** dtv_board_detect **********************************
* Returns TMLIBDEV_OK if the hardware appears to be a Philips dtv board.
*/
static tmLibdevErr_t dtv_ref3_board_detect(void)
{
Int line;
UInt32 d1, boardID, mfgID;
UInt8 eepromData[8];
for (line = 0; line < 8; line++) {
TRY(iicReadReg(IIC_EEPROM_ADDRESS, line, &d1));
eepromData[line] = d1;
}
mfgID = (eepromData[3] << 8) + eepromData[4];
boardID = (eepromData[1] << 8) + eepromData[2];
if (mfgID != BOARD_ID_PHILIPS_MFG_ID)
{
return BOARD_ERR_UNKNOWN_BOARD;
}
if (boardID == BOARD_VERSION_PHILIPS_DTV_REF3)
{
return TMLIBDEV_OK;
}
return BOARD_ERR_UNKNOWN_BOARD;
}
static tmLibdevErr_t dtv_ref3_board_register(pcomponent_t comp)
{
UInt32 ID = BOARD_VERSION_PHILIPS_DTV_REF3;
L1_DP(("dtv_ref3_board_register\n"));
TRY(tsaBoardRegisterAO(0, &dtv_ao));
TRY(tsaBoardRegisterVO(0, &dtv_vo));
TRY(tsaBoardRegisterSSI(0, &dtv_afe));
TRY(tsaBoardRegisterPIC(0, &dtvRef3PIC));
TRY(tsaBoardRegisterIR(0, &dtvRef3IR));
TRY(tsaBoardRegisterUart(0, &dtvRef3Uart1));
TRY(tsaBoardRegisterUart(1, &dtvRef3Uart2));
/* register the GOMAD board */
TRY(tsaBoardRegisterBoard(ID, "Philips DTVRef3"));
return TMLIBDEV_OK;
}
TSA_COMP_DEF_O_COMPONENT( Philips_dtv_ref3,
TSA_COMP_BUILD_ARG_LIST_2("bsp/boardID", "bsp/uart"),
dtv_ref3_board_activate);
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