📄 tda1315.h
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/*
* Copyright (c) 1995,1996,1997 by TriMedia Technologies.
*
* +------------------------------------------------------------------+
* | This software is furnished under a license and may only be used |
* | and copied in accordance with the terms and conditions of such |
* | a license and with the inclusion of this copyright notice. This |
* | software or any other copies of this software may not be provided|
* | or otherwise made available to any other person. The ownership |
* | and title of this software is not transferred. |
* | |
* | The information in this software is subject to change without |
* | any prior notice and should not be construed as a commitment by |
* | TriMedia Technologies. |
* | |
* | this code and information is provided "as is" without any |
* | warranty of any kind, either expressed or implied, including but |
* | not limited to the implied warranties of merchantability and/or |
* | fitness for any particular purpose. |
* +------------------------------------------------------------------+
*
* Module name : tda1315.h 1.6
*
* Last update : 18:43:48 - 00/11/09
*
* Description :
*
* Initialize and control routines for tda1315.
*
* Revision :
* Built for the TCS 1.1z release
*
*
*/
#ifndef _TDA1315_H
#define _TDA1315_H
#include <tm1/tmBoard.h>
#include "l3.h"
/* defines for getting information from the L3 registers of the TDA 1315 */
/* Channel status register:
BYTE1
0,1: Clock Accuracy
2,3: Sample frequency 00 = 44.1kHz, 01 = 48 kHz, 11 = 32 kHz
4 : Pre-emphasis
5 : copyright 0 = copyright, 1 = no copyright
6 : audio/data 0 = PCM, 1 = no PCM (e.g. AC-3)
7 : consumer/professional 0 = consumer use
Default value = 0xXX [xxxxxxxx]
BYTE2
0 : category code
1 : category code
2 : category code
3 : category code
4 : category code
5 : category code
6 : category code
7 : category code
Default value = 0xXX [xxxxxxxx]
*/
/* defines for byte 1: */
#define TDA1315_L3_CHAN_STAT_CLOCK_ACCURACY_MASK 0x03
#define TDA1315_L3_CHAN_STAT_FREQUENCY_MASK 0x0C
#define TDA1315_L3_CHAN_STAT_44100_HZ 0x00
#define TDA1315_L3_CHAN_STAT_48000_HZ 0x04
#define TDA1315_L3_CHAN_STAT_32000_HZ 0x0C
#define TDA1315_L3_CHAN_STAT_PRE_EMPH_MASK 0x10
#define TDA1315_L3_CHAN_STAT_PRE_EMPH_ON 0x10
#define TDA1315_L3_CHAN_STAT_PRE_EMPH_OFF 0x00
#define TDA1315_L3_CHAN_STAT_COPYRIGHT_MASK 0x20
#define TDA1315_L3_CHAN_STAT_COPYRIGHT 0x00
#define TDA1315_L3_CHAN_STAT_NO_COPYRIGHT 0x20
#define TDA1315_L3_CHAN_STAT_DATA_MASK 0x40
#define TDA1315_L3_CHAN_STAT_DATA 0x40
#define TDA1315_L3_CHAN_STAT_AUDIO 0x00
#define TDA1315_L3_CHAN_STAT_CONSUMER_MASK 0x80
#define TDA1315_L3_CHAN_STAT_CONSUMER 0x00
#define TDA1315_L3_CHAN_STAT_PROFESSIONAL 0x80
/* defines for byte 2: */
#define TDA1315_L3_CHAN_STAT_CATEGORY_MASK 0xFF
/* defines for the control register */
/* Control Register of L3 bus
BYTE1
0 : Transmit/receive mode: 0=transmit 1=receive
1 : Decode subcode Q-channel: 0=enable 1=disable
2,3: Number of bits to transfer:00=16bit 01=18bit 10=20bit 11=24bit
4 : Clear user data buffer: 0=clear 1=leave as is
5 : reserved
6 : reserved
7 : reserved
Default value = 0x02 [xxx00010]
BYTE2
0 : Audio mute: 0=enabled 1=disabled
1 : IEC output enable: 0=enabled 1=disabled
2 : Select IEC input: 0=TTL level 1=high sensitivity
3 : IIS output enable: 0=enabled 1=disabled
4 : Select IIS bus source: 0=SDAUX 1=SD
5 : Select clock frequency: 0=384fs 1=256fs
6 : reserved
7 : reserved
Default value = 0xF7 [11110111]
*/
/* defines for byte 1: */
#define TDA1315_L3_CONTROL_TRANS_REC_MASK 0x01
#define TDA1315_L3_CONTROL_TRANSMIT_MODE 0x00
#define TDA1315_L3_CONTROL_RECEIVE_MODE 0X01
#define TDA1315_L3_CONTROL_DECODE_SUBCODE_QCHAN_MASK 0x02
#define TDA1315_L3_CONTROL_DECODE_SUBCODE_QCHAN_ENABLE 0x00
#define TDA1315_L3_CONTROL_DECODE_SUBCODE_QCHAN_DISABLE 0x02
#define TDA1315_L3_CONTROL_NUMBER_OF_BITS_TO_TRANS_MASK 0x0c
#define TDA1315_L3_CONTROL_TRANSFER_16_BITS 0x00
#define TDA1315_L3_CONTROL_TRANSFER_18_BITS 0x04
#define TDA1315_L3_CONTROL_TRANSFER_20_BITS 0x08
#define TDA1315_L3_CONTROL_TRANSFER_24_BITS 0x0c
#define TDA1315_L3_CONTROL_CLEAR_USR_DATA_BUFFER_MASK 0x10
#define TDA1315_L3_CONTROL_LEAVE_USR_DATA_BUFFER 0x10
#define TDA1315_L3_CONTROL_CLEAR_USR_DATA_BUFFER 0x00
/* defines for byte 2: */
#define TDA1315_L3_CONTROL_MUTE_MASK 0x01
#define TDA1315_L3_CONTROL_MUTE 0x00
#define TDA1315_L3_CONTROL_UNMUTE 0x01
#define TDA1315_L3_CONTROL_IEC_OUTPUT_ENABLE_MASK 0x02
#define TDA1315_L3_CONTROL_IEC_OUTPUT_ENABLE 0x00
#define TDA1315_L3_CONTROL_IEC_OUTPUT_DISABLE 0x02
#define TDA1315_L3_CONTROL_IEC_INPUT_SELECT_MASK 0x04
#define TDA1315_L3_CONTROL_IEC_INPUT_SELECT_TTL 0x00
#define TDA1315_L3_CONTROL_IEC_INPUT_SELECT_HIGH_SENS 0x04
#define TDA1315_L3_CONTROL_IIS_OUTPUT_ENABLE_MASK 0x08
#define TDA1315_L3_CONTROL_IIS_OUTPUT_ENABLE 0x00
#define TDA1315_L3_CONTROL_IIS_OUTPUT_DISABLE 0x08
#define TDA1315_L3_CONTROL_IIS_SOURCE_SELECT_MASK 0x10
#define TDA1315_L3_CONTROL_IIS_SOURCE_SDAUX 0x00
#define TDA1315_L3_CONTROL_IIS_SOURCE_SD 0x10
#define TDA1315_L3_CONTROL_CLOCK_SELECT_MASK 0x20
#define TDA1315_L3_CONTROL_CLOCK_SELECT_384FS 0x00
#define TDA1315_L3_CONTROL_CLOCK_SELECT_256FS 0x20
#define TDA1315_L3_ADDRESS 0x01
typedef enum {
READ_CHANNEL_STATUS_REGISTER, /* mode 0 */
WRITE_CHANNEL_STATUS_REGISTER, /* mode 0 */
READ_USER_DATA_REGISTER, /* mode 1 */
WRITE_USER_DATA_REGISTER, /* mode 1 */
WRITE_CONTROL_REGISTER, /* mode 2 */
READ_STATUS_REGISTER, /* mode 3 */
} tda1315Register_t;
extern tmLibdevErr_t tda1315InitOutput(pl3Param_t l3Params, boardAOParam_t * param);
extern tmLibdevErr_t tda1315InitInput(pl3Param_t l3Params, boardAIParam_t * param);
extern tmLibdevErr_t tda1315AccessL3(pl3Param_t l3Params, tda1315Register_t mode);
#endif /*_TDA1315_H*/
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