l3.c

用于TM1300/PNX1300系列DSP（主要用于视频处理）的设备库的源码

/*
 * Copyright (c) 1999 by TriMedia Technologies. 
 *
 * +------------------------------------------------------------------+
 * | This software is furnished under a license and may only be used  |
 * | and copied in accordance with the terms and conditions of  such  |
 * | a license and with the inclusion of this copyright notice. This  |
 * | software or any other copies of this software may not be provided|
 * | or otherwise made available to any other person.  The ownership  |
 * | and title of this software is not transferred.                   |
 * |                                                                  |
 * | The information in this software is subject  to change without   |
 * | any  prior notice and should not be construed as a commitment by |
 * | TriMedia Technologies.                                           |
 * |                                                                  |
 * | this code and information is provided "as is" without any        |
 * | warranty of any kind, either expressed or implied, including but |
 * | not limited to the implied warranties of merchantability and/or  |
 * | fitness for any particular purpose.                              |
 * +------------------------------------------------------------------+
 *
 *  Module name              : l3.c    1.6
 *
 *  Last update              : 18:43:41 - 00/11/09
 *
 *
 */

#include <tm1/tmIIC.h>
#include <tm1/tmXIO.h>
#include <tm1/tmGPIO.h>
#include <tm1/tmAssert.h>

#include "l3.h"

#define L3_ADDRESS_CYCLE_LENGTH     8 
#define L3_READ_WRITE_CYCLE_LENGTH  8

static tmLibdevErr_t iicL3AddressPhase(pl3Param_t p)
{
    Int           i;
    Int           di         = 0;
    UInt          iicd;
    UInt32        iicAddress = p->address;
    UInt8         l3Address  = (UInt8) p->l3Address;
    UInt32        dataMask   = p->l3Data;
    UInt32        clockMask  = p->l3Clock;
    UInt32        modeMask   = p->l3Mode;
    UInt32        l3Mask;
    tmLibdevErr_t err;

    /* check pointers */
    tmAssert(p, -1);

    l3Mask = ~(clockMask | dataMask | modeMask);
 
    err = iicReadReg(iicAddress, -1, &iicd);
    tmAssert(err == TMLIBDEV_OK, err);
    iicd &= l3Mask;
    iicd |= dataMask | clockMask;
    err |= iicWriteReg(iicAddress, -1, iicd);
    tmAssert(err == TMLIBDEV_OK, err);

    for (i=0;i < L3_ADDRESS_CYCLE_LENGTH; i++)
    {
        err |= iicReadReg(iicAddress, -1, &iicd);
        tmAssert(err == TMLIBDEV_OK, err);
        iicd &= l3Mask;
        if (l3Address & (1 << di++))
        {
            iicd |= dataMask;
        }
        err |= iicWriteReg(iicAddress, -1, iicd);
        tmAssert(err == TMLIBDEV_OK, err);
        iicd |= clockMask;
        err |=iicWriteReg(iicAddress, -1, iicd);
        tmAssert(err == TMLIBDEV_OK, err);
    }
    
    err |= iicReadReg(iicAddress, -1, &iicd);
    tmAssert(err == TMLIBDEV_OK, err);
    iicd &= l3Mask;
    iicd |= modeMask | clockMask;
    err |= iicWriteReg(iicAddress, -1, iicd);
    tmAssert(err == TMLIBDEV_OK, err);
    return err;
}

static tmLibdevErr_t iicL3ReadPhase(pl3Param_t p)
{
    Int           i, j;
    Int           di;
    UInt          iicd;
    UInt8         l3Mask;
    UInt8         returnVal;
    UInt          iicAddress  = p->address;
    UInt          dataMask    = p->l3Data;
    UInt          clockMask   = p->l3Clock;
    UInt          modeMask    = p->l3Mode;
    tmLibdevErr_t err;
    
    /* check pointers */
    tmAssert(p, -1);
    tmAssert(p->data, -1);
    
    l3Mask = ~(clockMask | dataMask | modeMask);

    err = iicReadReg(iicAddress, -1, &iicd);
    tmAssert(err == TMLIBDEV_OK, err);
    iicd &= l3Mask;
    iicd |= modeMask | clockMask;
    err |= iicWriteReg(iicAddress, -1, iicd);
    tmAssert(err == TMLIBDEV_OK, err);

    for (j = 0; j < p->numberOfBytes; j++)
    {
        di        = 0;
        returnVal = 0;
        /* transfer one byte */
        for (i=0;i < L3_READ_WRITE_CYCLE_LENGTH; i++)
        {
            err |= iicReadReg(iicAddress, -1, &iicd);
            tmAssert(err == TMLIBDEV_OK, err);
            iicd &= l3Mask;
            iicd |= modeMask | dataMask;
            err |= iicWriteReg(iicAddress, -1, iicd);
            tmAssert(err == TMLIBDEV_OK, err);
            err |= iicReadReg(iicAddress, -1, &iicd);
            tmAssert(err == TMLIBDEV_OK, err);
            if (iicd & dataMask)
            {
                returnVal |= 0x1 << di;
            }
            di ++;
            iicd &= l3Mask;
            iicd |= modeMask | clockMask;
            err |= iicWriteReg(iicAddress, -1, iicd);
            tmAssert(err == TMLIBDEV_OK, err);
        }
        /* thalt - indicate end of byte transfer */
        err |= iicReadReg(iicAddress, -1, &iicd);
        tmAssert(err == TMLIBDEV_OK, err);
        iicd &= l3Mask;
        iicd |= clockMask;
        err |= iicWriteReg(iicAddress, -1, iicd);
        tmAssert(err == TMLIBDEV_OK, err);

        p->data[j] = (Char) returnVal;
    }
    
    /* put L3 bus into default state: mode and clock high */
    err |= iicReadReg(iicAddress, -1, &iicd);
    tmAssert(err == TMLIBDEV_OK, err);
    iicd &= l3Mask;
    iicd |= clockMask | modeMask;
    err |= iicWriteReg(iicAddress, -1, iicd);
    tmAssert(err == TMLIBDEV_OK, err);
    
    return err;
}

static tmLibdevErr_t iicL3WritePhase(pl3Param_t p)
{
    Int           i, j;
    Int           di;
    UInt          iicd;
    UInt8         l3Mask;
    UInt          iicAddress = p->address;
    UInt          dataMask   = p->l3Data;
    UInt          clockMask  = p->l3Clock;
    UInt          modeMask   = p->l3Mode;
    tmLibdevErr_t err;
    
    /* check pointers */
    tmAssert(p, -1);

    l3Mask = ~(clockMask | dataMask | modeMask);

    err = iicReadReg(iicAddress, -1, &iicd);
    tmAssert(err == TMLIBDEV_OK, err);
    iicd &= l3Mask;
    iicd |= modeMask | clockMask;
    err |= iicWriteReg(iicAddress, -1, iicd);
    tmAssert(err == TMLIBDEV_OK, err);

    for (j = 0; j < p->numberOfBytes; j++)
    {
        di = 0;
        for (i=0;i < L3_READ_WRITE_CYCLE_LENGTH; i++)
        {
            iicReadReg(iicAddress, -1, &iicd);
            tmAssert(err == TMLIBDEV_OK, err);
            iicd &= l3Mask;
            iicd |= modeMask;
            if (p->data[j] & (0x1 << di++))
            {
                iicd |= dataMask;
            }
            err |= iicWriteReg(iicAddress, -1, iicd);
            tmAssert(err == TMLIBDEV_OK, err);
            iicd |= clockMask;
            err |= iicWriteReg(iicAddress, -1, iicd);
            tmAssert(err == TMLIBDEV_OK, err);
        }
        /* thalt - indicate end of byte transfer */
        err |= iicReadReg(iicAddress, -1, &iicd);
        tmAssert(err == TMLIBDEV_OK, err);
        iicd &= l3Mask;
        iicd |= clockMask;
        err |= iicWriteReg(iicAddress, -1, iicd);
        tmAssert(err == TMLIBDEV_OK, err);
    }

    /* put L3 bus into default state: mode and clock high */
    err |= iicReadReg(iicAddress, -1, &iicd);
    tmAssert(err == TMLIBDEV_OK, err);
    iicd &= l3Mask;
    iicd |= clockMask | modeMask;
    err |= iicWriteReg(iicAddress, -1, iicd);
    tmAssert(err == TMLIBDEV_OK, err);

    return err;
}

static tmLibdevErr_t xioL3AddressPhase(pl3Param_t p)
{
    Int           i;
    Int           di         = 0;
    UInt8         l3Address  = (UInt8) p->l3Address;
    UInt32        dataMask   = p->l3Data;
    UInt32        clockMask  = p->l3Clock;
    UInt32        modeMask   = p->l3Mode;
    UInt32        dataAdd    = p->l3DataAdd;
    UInt32        clockAdd   = p->l3ClockAdd;
    UInt32        modeAdd    = p->l3ModeAdd;
    tmLibdevErr_t err;

    /* check pointers */
    tmAssert(p, -1);

    /* clock high */
    err = xioRegWriteBit(clockAdd, clockMask, True);
    tmAssert(err == TMLIBDEV_OK, err);

    /* mode low, stays low throughout the address phase */
    err |= xioRegWriteBit(modeAdd, modeMask, False);
    tmAssert(err == TMLIBDEV_OK, err);
       
    for (i=0;i < L3_ADDRESS_CYCLE_LENGTH; i++)
    {
        /* clock low */
        err |= xioRegWriteBit(clockAdd, clockMask, False);
        tmAssert(err == TMLIBDEV_OK, err);
        
        /* set data */
        if (l3Address & (1 << di++))
        {
            err |= xioRegWriteBit(dataAdd, dataMask, True);
            tmAssert(err == TMLIBDEV_OK, err);
        }
        else
        {
            err |= xioRegWriteBit(dataAdd, dataMask, False);
            tmAssert(err == TMLIBDEV_OK, err);
        }
        /* clock high */
        err |= xioRegWriteBit(clockAdd, clockMask, True);
        tmAssert(err == TMLIBDEV_OK, err);
    }
    
    /* set mode high again */
    err |= xioRegWriteBit(modeAdd, modeMask, True);
    tmAssert(err == TMLIBDEV_OK, err);

    return err;
}

static tmLibdevErr_t xioL3WritePhase(pl3Param_t p)
{
    Int           i, j;
    Int           di         = 0;
    UInt32        dataMask   = p->l3Data;
    UInt32        clockMask  = p->l3Clock;
    UInt32        modeMask   = p->l3Mode;
    UInt32        dataAdd    = p->l3DataAdd;
    UInt32        clockAdd   = p->l3ClockAdd;
    UInt32        modeAdd    = p->l3ModeAdd;
    tmLibdevErr_t err;
    
    /* check pointers */
    tmAssert(p, -1);

    /* mode high */
    err = xioRegWriteBit(modeAdd, modeMask, True);
    tmAssert(err == TMLIBDEV_OK, err);

    for (j = 0; j < p->numberOfBytes; j++)
    {
        di = 0;
        for (i=0;i < L3_READ_WRITE_CYCLE_LENGTH; i++)
        {
            /* clock low */
            err = xioRegWriteBit(clockAdd, clockMask, False);
            tmAssert(err == TMLIBDEV_OK, err);
            
            /* data */
            if (p->data[j] & (0x1 << di++))
            {
                err |= xioRegWriteBit(dataAdd, dataMask, True);
                tmAssert(err == TMLIBDEV_OK, err);
            }
            else
            {
                err |= xioRegWriteBit(dataAdd, dataMask, False);
                tmAssert(err == TMLIBDEV_OK, err);
            }
            /* clock high */
            err = xioRegWriteBit(clockAdd, clockMask, True);
            tmAssert(err == TMLIBDEV_OK, err);
        }
        /* indicate end of byte transfer */
        /* mode low */
        err |= xioRegWriteBit(modeAdd, modeMask, False);
        tmAssert(err == TMLIBDEV_OK, err);
        /* mode high */
        err |= xioRegWriteBit(modeAdd, modeMask, True);
        tmAssert(err == TMLIBDEV_OK, err);
    }

    return err;
}

static tmLibdevErr_t gpioL3AddressPhase(pl3Param_t p)
{
    Int           i;
    Int           di         = 0;
    UInt8         l3Address  = (UInt8) p->l3Address;
    UInt32        temp;  
    UInt32        dataMask   = p->l3Data;
    UInt32        clockMask  = p->l3Clock;
    UInt32        modeMask   = p->l3Mode;
    tmLibdevErr_t err = TMLIBDEV_OK;

    /* check pointers */
    tmAssert(p, -1);

    /* mode low, stays low throughout the address phase */
    /* clock high, Mode low  */
    temp = MMIO(GPIOJ_OUT);
    temp &= (~(clockMask | modeMask ));
    temp |= clockMask;
    MMIO(GPIOJ_OUT) = temp;

    microsleep(50);

    for (i=0;i < L3_ADDRESS_CYCLE_LENGTH; i++)
    {
        /* clock low */
        temp = MMIO(GPIOJ_OUT);
        temp &= ~clockMask;
        MMIO(GPIOJ_OUT) = temp;
        
        microsleep(50);

        /* set data */
        if (l3Address & (1 << di++))
        {
            /* Set Data  high */
            temp = MMIO(GPIOJ_OUT);
            temp &= ~dataMask;
            MMIO(GPIOJ_OUT) = temp | dataMask;
        }
        else
        {
            /* Set Data low */
            temp = MMIO(GPIOJ_OUT);
            temp &= ~dataMask;
            MMIO(GPIOJ_OUT) = temp;
        }
        microsleep(50);
        /* clock high */
        temp = MMIO(GPIOJ_OUT);
        temp &= ~clockMask;
        MMIO(GPIOJ_OUT) = temp | clockMask;
        microsleep(50);
    }
    
    /* set mode high again */
    temp = MMIO(GPIOJ_OUT);
    temp &= ~modeMask;
    MMIO(GPIOJ_OUT) = temp | modeMask;
    microsleep(50);

    return err;
}

static tmLibdevErr_t gpioL3WritePhase(pl3Param_t p)
{
    Int           i, j;
    Int           di         = 0;
    UInt32        temp;
    UInt32        dataMask   = p->l3Data;
    UInt32        clockMask  = p->l3Clock;
    UInt32        modeMask   = p->l3Mode;
    tmLibdevErr_t err = 0;
    
    /* check pointers */
    tmAssert(p, -1);

    /* mode high */
    temp = MMIO(GPIOJ_OUT);
    temp &= ~modeMask;
    MMIO(GPIOJ_OUT) = temp | modeMask;

    for (j = 0; j < p->numberOfBytes; j++)
    {
        di = 0;
        for (i=0;i < L3_READ_WRITE_CYCLE_LENGTH; i++)
        {
            /* clock low */
            temp = MMIO(GPIOJ_OUT);
            temp &= ~clockMask;
            MMIO(GPIOJ_OUT) = temp;

            /* data */
            if (p->data[j] & (0x1 << di++))
            {
                /* data high */
                temp = MMIO(GPIOJ_OUT);
                temp &= ~dataMask;
                MMIO(GPIOJ_OUT) = temp | dataMask;
            }
            else
            {
                /* data low */
                temp = MMIO(GPIOJ_OUT);
                temp &= ~dataMask;
                MMIO(GPIOJ_OUT) = temp;
            }
            /* clock high */
            temp = MMIO(GPIOJ_OUT);
            temp &= ~clockMask;
            MMIO(GPIOJ_OUT) = temp | clockMask;
        }
        /* indicate end of byte transfer */
        /* mode low */
        temp = MMIO(GPIOJ_OUT);
        temp &= ~modeMask;
        MMIO(GPIOJ_OUT) = temp;
        /* some delay is required */
        /* mode high */
        temp = MMIO(GPIOJ_OUT);
        temp &= ~modeMask;
        MMIO(GPIOJ_OUT) = temp | modeMask;
    }

    return err;
}



extern tmLibdevErr_t l3Write(pl3Param_t p)
{
    tmLibdevErr_t rVal;
    
    tmAssert(p, -1);
    
    switch (p->mode)
    {
    case l3ModeIIC:
        rVal = iicL3AddressPhase(p);
        rVal = iicL3WritePhase(p);
        break;
    case l3ModeXIO:
        rVal = xioL3AddressPhase(p);
        rVal = xioL3WritePhase(p);
        break;
    case l3ModeGPIO:
        rVal = gpioL3AddressPhase(p);
        rVal = gpioL3WritePhase(p);
        break;
    default:
        return L3_ERR_MODE_NOT_SUPPORTED;
    }
    
    return rVal;
}

extern tmLibdevErr_t l3Read(pl3Param_t p)
{
    tmLibdevErr_t rVal;
    
    tmAssert(p, -1);
    tmAssert(p->data, -1);
    
    switch (p->mode)
    {
    case l3ModeIIC:
        rVal = iicL3AddressPhase(p);
        rVal = iicL3ReadPhase(p);
        break;
    case l3ModeGPIO:
    case l3ModeXIO:
    default:
        return L3_ERR_MODE_NOT_SUPPORTED;
    }
    
    return rVal;
}