w83977atf.c

用于TM1300/PNX1300系列DSP（主要用于视频处理）的设备库的源码

        WriteCR(W83977ATF_SEL_LDEV, 2); /* UART A */
        baseAddress = uartPort0BaseAddress;
        irq         = uartPort0IRQ;
    }
    else
    {
        WriteCR(W83977ATF_SEL_LDEV, 3); /* UART B */
        baseAddress = uartPort1BaseAddress;
        irq         = uartPort1IRQ;
    }

    WriteCR(0x60, (UInt8) (baseAddress >> 8));   /* UART base IO address*/
    WriteCR(0x61, (UInt8) (baseAddress & 0xff));
    WriteCR(0x70, irq);                          /* set IRQ */

    WriteCR(0xf0, 0x03); /* enable 14.769 MHz mode */
    WriteCR(0x30, 0x01); /* Activate logical device */

    ExitExtFnMode();     /* Exit extended function mode */

    err = w83977atfUartSetBaudRate(portID, params->baudRate);
    if (err)
        return err;

    err = w83977atfUartSetSerialDataFormat(portID, params->numStopBits, params->numDataBits, params->parity);
    if (err)
        return err;

    err = w83977atfUartSetTxInt(portID, False);
    if (err)
        return err;

    err = w83977atfUartSetRxInt(portID, False);
    if (err)
        return err;

    err = w83977atfUartSetLineStatusInt(portID, False);
    if (err)
        return err;

    err = w83977atfUartSetModemStatusInt(portID, params->enableControlInt);
    if (err)
        return err;

    err = w83977atfUartSetInt(portID, True);
    if (err)
        return err;

    return TMLIBDEV_OK;
}

/************************************************************************************************/
extern tmLibdevErr_t w83977atfUartTermPort(unitSelect_t portID)
{
    tmLibdevErr_t err;

    err = w83977atfUartSetInt(portID, False);
    if (err)
        return err;

    EnterExtFnMode(); /* Enter extended function mode */

    if (portID == unit0)
    {
        WriteCR(W83977ATF_SEL_LDEV, 2); /* UART A */
    }
    else
    {
        WriteCR(W83977ATF_SEL_LDEV, 3); /* UART B */
    }

    WriteCR(0x30, 0x00); /* Disable logical device */

    ExitExtFnMode();     /* Exit extended function mode */

    return TMLIBDEV_OK;
}

/************************************************************************************************/
extern tmLibdevErr_t w83977atfUartSetBaudRate(unitSelect_t portID, tsaUartBaud_t baudRate)
{
    UInt8 reg1;
    UInt8 reg2;
    UInt8 reg3;
    Int   i;

    /* get index for baudrate table */
    switch(baudRate)
    {
    case UART_BAUD_9600:
        i = 0;
        break;
    case UART_BAUD_14400:
        i = 1;
        break;
    case UART_BAUD_19200:
        i = 2;
        break;
    case UART_BAUD_38400:
        i = 3;
        break;
    case UART_BAUD_57600:
        i = 4;
        break;
    case UART_BAUD_115200:
        i = 5;
        break;
    case UART_BAUD_230400:
        i = 6;
        break;
    case UART_BAUD_460800:
        i = 7;
        break;
    case UART_BAUD_921600:
        i = 8;
        break;
    default:
        return UART_ERR_INVALID_BAUDRATE;
    }

    /* Set divisor latch access bit, so that the divisor latch of the baud generator
       can be accessed. */
    reg1 = uartReadByte(portID, W83977ATF_UART_UCR) | 0x80;
    uartWriteByte(portID, W83977ATF_UART_UCR, reg1);

    reg2 = baudTable[i] & 0xff;
    reg3 = baudTable[i] >> 8;

    uartWriteByte(portID, W83977ATF_UART_BLL, reg2);
    uartWriteByte(portID, W83977ATF_UART_BHL, reg3);
    
    /* reset divisor latch access bit */
    reg1 &= 0x7f;
    uartWriteByte(portID, W83977ATF_UART_UCR, reg1);

    return TMLIBDEV_OK;
}

/************************************************************************************************/
extern tmLibdevErr_t w83977atfUartSetSerialDataFormat(unitSelect_t portID, Int numStopBits, Int numDataBits, tsaUartParity_t parity)
{
    UInt8 reg;

    reg = uartReadByte(portID, W83977ATF_UART_UCR) & 0xe0;

    switch(numStopBits)
    {
    case 1:
        break;
    case 2:
        reg |= 0x04;
        break;
    default:
        return UART_ERR_INVALID_NUM_STOP_BITS;
    }

    switch(numDataBits)
    {
    case 5:
        break;
    case 6:
        reg |= 0x01;
        break;
    case 7:
        reg |= 0x02;
        break;
    case 8:
        reg |= 0x03;
        break;
    default:
        return UART_ERR_INVALID_NUM_DATA_BITS;
    }

    switch(parity)
    {
    case UART_PARITY_NONE:
        break;
    case UART_PARITY_EVEN:
        reg |= 0x18;
        break;
    case UART_PARITY_ODD:
        reg |= 0x08;
        break;
    default:
        return UART_ERR_INVALID_PARITY;
    }

    uartWriteByte(portID, W83977ATF_UART_UCR, reg);

    return TMLIBDEV_OK;
}

/************************************************************************************************/
extern tmLibdevErr_t w83977atfUartSetTxInt(unitSelect_t portID, Bool enable)
{
    Int8 reg;
    
    reg = uartReadByte(portID, W83977ATF_UART_ICR);
    
    if (enable)
        reg |= 0x02;
    else
        reg &= 0xfd;

    uartWriteByte(portID, W83977ATF_UART_ICR, reg);

    return TMLIBDEV_OK;
}

/************************************************************************************************/
extern tmLibdevErr_t w83977atfUartSetRxInt(unitSelect_t portID, Bool enable)
{
    Int8 reg;
    
    reg = uartReadByte(portID, W83977ATF_UART_ICR);
    
    if (enable)
        reg |= 0x01;
    else
        reg &= 0xfe;

    uartWriteByte(portID, W83977ATF_UART_ICR, reg);

    return TMLIBDEV_OK;
}

/************************************************************************************************/
extern tmLibdevErr_t w83977atfUartSetLineStatusInt(unitSelect_t portID, Bool enable)
{
    Int8 reg;
    
    reg = uartReadByte(portID, W83977ATF_UART_ICR);
    
    if (enable)
        reg |= 0x04;
    else
        reg &= 0xfb;

    uartWriteByte(portID, W83977ATF_UART_ICR, reg);

    return TMLIBDEV_OK;
}

/************************************************************************************************/
extern tmLibdevErr_t w83977atfUartSetModemStatusInt(unitSelect_t portID, Bool enable)
{
    Int8 reg;
    
    reg = uartReadByte(portID, W83977ATF_UART_ICR);
    
    if (enable)
        reg |= 0x08;
    else
        reg &= 0xf7;

    uartWriteByte(portID, W83977ATF_UART_ICR, reg);

    return TMLIBDEV_OK;
}

/************************************************************************************************/
extern tmLibdevErr_t w83977atfUartReadData(unitSelect_t portID, Address data)
{
    *data = uartReadByte(portID, W83977ATF_UART_RBR);

    return TMLIBDEV_OK;
}

/************************************************************************************************/
extern tmLibdevErr_t w83977atfUartWriteData(unitSelect_t portID, Char data)
{
    uartWriteByte(portID, W83977ATF_UART_TBR, data);

    return TMLIBDEV_OK;
}

/************************************************************************************************/
extern tmLibdevErr_t w83977atfUartConfig(unitSelect_t portID, tsaUartConfig_t command, Pointer value)
{
    UInt8         reg1;
    tmLibdevErr_t err = TMLIBDEV_OK;

    switch (command)
    {
    case UART_DTR_ON:
        reg1 = uartReadByte(portID, W83977ATF_UART_HCR) | 0x01;
        uartWriteByte(portID, W83977ATF_UART_HCR, reg1);
    break;
    case UART_DTR_OFF:
        reg1 = uartReadByte(portID, W83977ATF_UART_HCR) & 0xfe;
        uartWriteByte(portID, W83977ATF_UART_HCR, reg1);
    break;
    case UART_RTS_ON:
        reg1 = uartReadByte(portID, W83977ATF_UART_HCR) | 0x02;
        uartWriteByte(portID, W83977ATF_UART_HCR, reg1);
    break;
    case UART_RTS_OFF:
        reg1 = uartReadByte(portID, W83977ATF_UART_HCR) & 0xfd;
        uartWriteByte(portID, W83977ATF_UART_HCR, reg1);
    break;
    case UART_GET_SCRATCH_REGI:
        tmAssert(value, TMLIBDEV_ERR_NULL_PARAMETER);
        *(UInt8*)value = uartReadByte(portID, W83977ATF_UART_UDR);
    break;
    case UART_SET_SCRATCH_REGI:
        tmAssert(value, TMLIBDEV_ERR_NULL_PARAMETER);
        uartWriteByte(portID, W83977ATF_UART_UDR, *(UInt8*)value);
    break;
    case UART_SET_LOOP_BACK:
        reg1 = uartReadByte(portID, W83977ATF_UART_HCR) & 0xef;
        if (*(Bool *) value)
            reg1 |= 0x10;
        uartWriteByte(portID, W83977ATF_UART_HCR, reg1);
    break;
    default:
        return UART_ERR_UNSUPPORTED_CONFIG_COMMAND;
    }

    return err;
}

/************************************************************************************************/
extern Bool w83977atfUartGetEvent(unitSelect_t portID, tsaUartConfigEvent_t *event)
{
    UInt8  reg;
    UInt8  reg2;
    UInt32 e;

    if (uartIsrStore == 0)
        reg = uartReadByte(portID, W83977ATF_UART_ISR) & 0x0f;
    else
    {
        reg      = uartIsrStore;
        uartIsrStore = 0;
    }

    if (reg & 0x01)
    {
        return False;
    }
    
    switch (reg)
    {
    case 0x06:
        e    = BOARD_UART_ERR_EVENT;
        reg2 = uartReadByte(portID, W83977ATF_UART_USR);
        if (reg2 & 0x02)
            e |= BOARD_UART_RX_ERR_OVERRUN;
        if (reg2 & 0x04)
            e |= BOARD_UART_RX_ERR_PARITY;
        if (reg2 & 0x08)
            e |= BOARD_UART_RX_ERR_FRAMING;
        if (reg2 & 0x10)
            e |= BOARD_UART_RX_ERR_BREAK;
        break;
    case 0x04:
        e = BOARD_UART_RX_DATA;
        break;
    case 0x0c:
        e = BOARD_UART_RX_DATA;
        break;
    case 0x02:
        e = BOARD_UART_TX_COMPLETE;
        break;
    case 0x00:
        e = BOARD_UART_CONFIG_EVENT;
        reg2 = uartReadByte(portID, W83977ATF_UART_HSR);
        if (reg2 & 0x01)
        {
            if (reg2 & 0x10)
                e |= UART_CTS_ON;
            else
                e |= UART_CTS_OFF;
        }
        if (reg2 & 0x02)
        {
            if (reg2 & 0x20)
                e |= UART_DSR_ON;
            else
                e |= UART_DSR_OFF;
        }
        if (reg & 0x04)
            e |= UART_RI_OFF;
        if (reg & 0x08)
        {
            if (reg2 & 0x20)
                e |= UART_DCD_ON;
            else
                e |= UART_DCD_OFF;
        }
        if (reg & 0x80)
            e |= UART_RI_ON;
        break;
    default:
        e = BOARD_UART_ERR_OTHER;
        break;
    }

    *event = e;

    return True;
}