📄 philips_dtv_ref4.c
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{
"HDVO1",
&dtvRef4_HDVO_Init,
&dtvRef4_HDVO_Term,
&dtvRef4_HDVO_Config,
vas1920x1080 | vas720x480p,
vaaGeneric,
vtfRGB | vtfYUV,
hdvoImageOutput_30b_444,
vdfAspectRatio_16x9 | vdfInterlaced | vdfProgressive,
intHDVO,
GPIO_HDVO_CLK,
GPIO_HDVO_D29
};
static boardMPConfig_t dtvRef4_mp =
{
intMPEG,
MP_VLD_COMMAND, /* mmio base offset of pipe */
};
volatile static UInt32 *sioBaseAddress = (UInt32*) DTV_REF4_XIO_SIO_BASE;
volatile static UInt32 *p1394BaseAddress = (UInt32*) DTV_REF4_XIO_1394_BASE;
/***********************************************************************/
static tmLibdevErr_t ref4SioWrite (UInt32 sioAddress, UInt8 data)
{
tmLibdevErr_t err;
err = dtvRef4_bankSwitch(DTV_REF4_XIO_SIO_BANK);
if (err)
return err;
xioSimpleWrite(DTV_REF4_XIO_SIO_BASE + (sioAddress << 2), data);
return TMLIBDEV_OK;
}
/***********************************************************************/
static tmLibdevErr_t ref4SioRead (UInt32 sioAddress, UInt32 *data)
{
tmLibdevErr_t err;
err = dtvRef4_bankSwitch(DTV_REF4_XIO_SIO_BANK);
if (err)
return err;
*data = (UInt32) xioSimpleRead(DTV_REF4_XIO_SIO_BASE + (sioAddress << 2));
return TMLIBDEV_OK;
}
/*
* The following two functions are used to read/write from/to the 1394
* registers. The address offset is the offset from 1394's base address.
*/
/***********************************************************************/
static tmLibdevErr_t ref4P1394Write (UInt32 addressOffset, UInt8 data)
{
tmLibdevErr_t err;
err = dtvRef4_bankSwitch(DTV_REF4_XIO_1394_BANK);
if (err)
return err;
xioSimpleWrite(DTV_REF4_XIO_1394_BASE + (addressOffset << 2), data);
return TMLIBDEV_OK;
}
/***********************************************************************/
static tmLibdevErr_t ref4P1394Read (UInt32 addressOffset, UInt8 *data)
{
tmLibdevErr_t err;
err = dtvRef4_bankSwitch(DTV_REF4_XIO_1394_BANK);
if (err)
return err;
*data = (UInt32) xioSimpleRead(DTV_REF4_XIO_1394_BASE + (addressOffset << 2));
return TMLIBDEV_OK;
}
/***********************************************************************/
static tmLibdevErr_t dtvRef4DirectionSwitch(UInt32 direction)
{
UInt32 val = MMIO(GPIOJ_OUT) & ~DTV_REF4_IIC_DIRECTION_MASK;
switch (direction)
{
case IIC_DIRECTION_BOOT_ROM:
val |= DTV_REF4_IIC_DIRECTION_BOOT;
break;
case IIC_DIRECTION_RTC:
val |= DTV_REF4_IIC_DIRECTION_RTC;
break;
case IIC_DIRECTION_NIM1:
val |= DTV_REF4_IIC_DIRECTION_NIM1;
break;
case IIC_DIRECTION_NIM2:
val |= DTV_REF4_IIC_DIRECTION_NIM2;
break;
default:
return 1;
}
MMIO(GPIOJ_OUT) = val;
return TMLIBDEV_OK;
}
/***********************************************************************/
static tmLibdevErr_t dtvRef4_bankSwitch(UInt32 bank)
{
UInt val;
static UInt32 currentBank = 0xffffffff;
if (currentBank == bank)
return TMLIBDEV_OK;
if (boardID == BOARD_VERSION_PHILIPS_DTV_REF4)
{
if (currentBank == 0xffffffff)
{
TRY(iicWriteReg(DTV_REF4_IIC_EXPANDER_ADDRESS, -1, 0xff));
TRY(iicReadReg(DTV_REF4_IIC_EXPANDER_ADDRESS, -1, &val));
currentBank = val & 0x03;
}
if ((bank & DTV_REF4_XIO_BK0) != (currentBank & DTV_REF4_XIO_BK0))
{
TRY(iicWriteReg(DTV_REF4_IIC_EXPANDER_ADDRESS, -1, 0xff));
TRY(iicWriteReg(DTV_REF4_IIC_EXPANDER_ADDRESS, -1, 0xbf));
TRY(iicWriteReg(DTV_REF4_IIC_EXPANDER_ADDRESS, -1, 0xff));
}
if ((bank & DTV_REF4_XIO_BK1) != (currentBank & DTV_REF4_XIO_BK1))
{
TRY(iicWriteReg(DTV_REF4_IIC_EXPANDER_ADDRESS, -1, 0xff));
TRY(iicWriteReg(DTV_REF4_IIC_EXPANDER_ADDRESS, -1, 0x7f));
TRY(iicWriteReg(DTV_REF4_IIC_EXPANDER_ADDRESS, -1, 0xff));
}
}
else
{
val = MMIO(GPIOJ_OUT);
val &= ~DTV_REF4_GPIO_BK_MASK;
switch (bank)
{
case DTV_REF4_XIO_REG_BANK:
val |= DTV_REF4_GPIO_BK1;
break;
case DTV_REF4_XIO_FLASH_BANK:
val |= DTV_REF4_GPIO_BK0 | DTV_REF4_GPIO_BK1;
break;
}
MMIO(GPIOJ_OUT) = val;
}
currentBank = bank;
return TMLIBDEV_OK;
}
/*
* Function to switch the 1394 Isochronous transmission path.
*/
/***********************************************************************/
static tmLibdevErr_t dtvRef4_muxSwitch(UInt32 muxConfig)
{
/*
* for A\V data from VSB to 1394 : xioRegWriteByte(0x06, 0x00);
* for A\V data from SDVO to 1394 : xioRegWriteByte(0x06, 0x40);
* for A\V data from 1394 to VI2 : xioRegWriteByte(0x06, 0xe0);
*/
switch(muxConfig)
{
case DTV_1394_MUX_CPU_BYPASS_MODE:
xioRegWriteByte(0x06, 0x00);
break;
case DTV_1394_MUX_RECORD_MODE:
xioRegWriteByte(0x06, 0x40);
break;
case DTV_1394_MUX_PLAY_MODE:
xioRegWriteByte(0x06, 0xe0);
break;
default:
break;
}
return TMLIBDEV_OK;
}
/***********************************************************************/
static void dtvRef4_AVReset()
{
UInt32 i ;
/* Reset 1394 chips */
for(i=0; i<5; i++)
{
xioRegWriteByte(0x5, 0xfa);
microsleep(300000);
xioRegWriteByte(0x5, 0xfe);
microsleep(300000);
xioRegWriteByte(0x5, 0xfa);
microsleep(300000);
}
}
/* PIC functions */
static UInt32 gpioj15EventInitCount = 0;
static UInt32 gpioj17EventInitCount = 0;
#define REF4_COM1_IRQ 0x04
#define REF4_COM2_IRQ 0x03
#define REF4_IR_IRQ 0x05
#define REF4_GPIO_SIO_EVENT 0x0
#define REF4_GPIO_PLD_EVENT 0x1
#if 0
static UInt8 ref4IrqArray[DTV_REF4_PIC_NUM_SRCS] =
{
REF4_COM1_IRQ,
REF4_COM2_IRQ,
REF4_IR_IRQ
};
#endif
static Int gpioJ15instance;
static Int gpioJ17instance;
/* from source number, get super IO source */
static UInt8 ref4Irq2SrcArray[16] =
{
0xff,
0xff,
0xff,
DTV_REF4_PIC_SOURCE_COMM2,
DTV_REF4_PIC_SOURCE_COMM1,
DTV_REF4_PIC_SOURCE_IR_IN0,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff
};
static tmLibdevErr_t dtvRef4PICInit(UInt32 source)
{
tmLibdevErr_t err;
gpioInstanceSetup_t gpioSetup;
DP_R4(("dtvRef4PICInit(%d)\n", source));
/* DP_R4(("disable all peripheral ints\n")); */
xioRegWriteByte (0x0A, 0x00);
switch (source)
{
case DTV_REF4_PIC_SOURCE_COMM1:
case DTV_REF4_PIC_SOURCE_COMM2:
case DTV_REF4_PIC_SOURCE_IR_IN0:
{
if (gpioj15EventInitCount == 0)
{
DP_R4(("open GPIO 15\n"));
/* Open GPIO pin */
err = gpioOpen(&gpioJ15instance);
if (err)
return err;
err = gpioGetInstanceSetup(gpioJ15instance, &gpioSetup);
if (err)
{
gpioClose(gpioJ15instance);
return err;
}
gpioInsertMode(gpioSetup.pinMode[GPIO_GPIOJ15 >> 4],
GPIO_GPIOJ15 & 0x0f,
gpioRegularMode);
gpioInsertPin(gpioSetup.pinMask[GPIO_GPIOJ15 >> 5],
GPIO_GPIOJ15 & 0x1f,
1);
err = gpioInstanceSetup(gpioJ15instance, &gpioSetup);
if (err)
{
gpioClose(gpioJ15instance);
return err;
}
/* Initialize event handler for GPIOJ15. This pin uses event 1. */
gpioSetSOURCE_SEL(REF4_GPIO_SIO_EVENT, GPIO_GPIOJ15);
gpioEnableEV_INTEN(REF4_GPIO_SIO_EVENT);
if (boardID == BOARD_VERSION_PHILIPS_DTV_REF4)
gpioSetEVENT_MODE(REF4_GPIO_SIO_EVENT, 0x02);
else
gpioSetEVENT_MODE(REF4_GPIO_SIO_EVENT, 0x01);
}
gpioj15EventInitCount++;
break;
}
case DTV_REF4_PIC_SOURCE_AUDIO1:
case DTV_REF4_PIC_SOURCE_AUDIO2:
case DTV_REF4_PIC_SOURCE_1394:
{
if (gpioj17EventInitCount == 0)
{
tsaRegEntryClass_t entryType;
ptsaRegDataEntry_t entry;
UInt8 data8;
DP_R4(("open GPIO 17\n"));
/* check whether NIM is installed */
err = tsaRegQuery("bsp/daughterboard/00/NIM board", &entryType, (Pointer *)&entry);
if (err != TMLIBDEV_OK || entryType != recData || entry->dataType != redtChar)
{
NimInstalled = False;
DP_R4(("No NIM\n"));
} else {
UInt32 iicd;
NimInstalled = True;
xioRegReadByte(0x4, &data8);
DP_R4(("Read %x from xio status\n", data8));
iicReadReg(NIM_SPDIF_STATUS_ADDRESS, -1, &iicd);
DP_R4(("Nim Installed, %x\n", iicd));
xioRegReadByte(0x4, &data8);
DP_R4(("Read %x from xio status after iic read\n", data8));
}
/* Open GPIO pin */
err = gpioOpen(&gpioJ17instance);
if (err)
return err;
err = gpioGetInstanceSetup(gpioJ17instance, &gpioSetup);
if (err)
{
gpioClose(gpioJ17instance);
return err;
}
gpioInsertMode(gpioSetup.pinMode[GPIO_GPIOJ17 >> 4],
GPIO_GPIOJ17 & 0x0f,
gpioRegularMode);
gpioInsertPin(gpioSetup.pinMask[GPIO_GPIOJ17 >> 5],
GPIO_GPIOJ17 & 0x1f,
1);
err = gpioInstanceSetup(gpioJ17instance, &gpioSetup);
if (err)
{
gpioClose(gpioJ17instance);
return err;
}
/* Initialize event handler for GPIOJ17. This pin uses event 1. */
gpioSetSOURCE_SEL(REF4_GPIO_PLD_EVENT, GPIO_GPIOJ17);
gpioSetEVENT_MODE(REF4_GPIO_PLD_EVENT, 0x1); /* "negative" edge */
gpioEnableEV_INTEN(REF4_GPIO_PLD_EVENT);
}
gpioj17EventInitCount++;
break;
}
default:
return PIC_ERR_SOURCE_NOT_AVAILABLE;
}
return TMLIBDEV_OK;
}
static tmLibdevErr_t dtvRef4PICTerm(UInt32 source)
{
DP_R4(("dtvRef4PICTerm(%d)\n", source));
switch (source)
{
case DTV_REF4_PIC_SOURCE_COMM1:
case DTV_REF4_PIC_SOURCE_COMM2:
case DTV_REF4_PIC_SOURCE_IR_IN0:
if (gpioj15EventInitCount == 1)
{
DP_R4(("close GPIO 15\n"));
/* Reset event handler for GPIOJ15. This pin uses event 1. */
gpioDisableEV_INTEN(REF4_GPIO_SIO_EVENT);
}
gpioj15EventInitCount--;
break;
case DTV_REF4_PIC_SOURCE_AUDIO1:
case DTV_REF4_PIC_SOURCE_AUDIO2:
case DTV_REF4_PIC_SOURCE_1394:
if (gpioj17EventInitCount == 1)
{
DP_R4(("close GPIO 17\n"));
if (IicInstance != 0) {
iicClose(IicInstance);
IicInstance = 0;
}
/* Reset event handler for GPIOJ17. This pin uses event 1. */
gpioDisableEV_INTEN(REF4_GPIO_PLD_EVENT);
}
gpioj17EventInitCount--;
break;
default:
DP_R4(("PIC_ERR_SOURCE_NOT_AVAILABLE: %d requested\n", source));
return PIC_ERR_SOURCE_NOT_AVAILABLE;
}
return TMLIBDEV_OK;
}
/* called multiple times, as long as True is returned.
* allows priorization.
* fill in source to indicate which Int to process
*/
static Bool dtvRef4PICSourceDetect(UInt32 * source)
{
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