📄 tmpci.c
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/*
* Copyright (c) 1998,2000 TriMedia Technologies Inc.
*
* +------------------------------------------------------------------+
* | This software is furnished under a license and may only be used |
* | and copied in accordance with the terms and conditions of such |
* | a license and with the inclusion of this copyright notice. This |
* | software or any other copies of this software may not be provided|
* | or otherwise made available to any other person. The ownership |
* | and title of this software is not transferred. |
* | |
* | The information in this software is subject to change without |
* | any prior notice and should not be construed as a commitment by |
* | TriMedia Technologies. |
* | |
* | this code and information is provided "as is" without any |
* | warranty of any kind, either expressed or implied, including but |
* | not limited to the implied warranties of merchantability and/or |
* | fitness for any particular purpose. |
* +------------------------------------------------------------------+
*
* Module name : tmPCI 2.00
*
*
* Description :
* Trimedia PCI library.
*
* This file provides functions for enabling and disabling PCI
* accesses from the TriMedia Processor.
* Integrated DTV specific PCI routines to this file.
*
*/
/*----------------------------- includes ------------------------------------*/
#include <tmlib/tmtypes.h>
#include <tm1/mmio.h>
#include <tm1/tmInterrupts.h>
#include <tm1/tmLibdevErr.h>
#include <tm1/tmDMA.h>
#include <tm1/tmPCI.h>
#include "stdio.h"
/*#define PRINTF(_x_) printf _x_ */
#define PRINTF(_x_)
/*------------------------- local definitions -------------------------------*/
/* Move this stuff to tmLinDevErr.h */
#define Err_base_PCI ( ERR_LAYER_LIBDEV | ERR_TYPE_OTHER | 0x80000 )
#define PCI_ERR_SDRAM_RANGE ( Err_base_PCI + 0x1 )
#define PCI_ERR_ALIGNMENT ( Err_base_PCI + 0x2 )
#define DCACHE_PAGE_SIZE (0x40)
#define PCI_DC_LOCK_MASK 0x03
#define PCI_DC_LOCK_SHIFT 0x05
#define PCI_DC_LOCK (PCI_DC_LOCK_MASK << PCI_DC_LOCK_SHIFT)
#define PCI_DC_LOCK_CTL_HEN 0x0 /* HOLE ENABLE + PCI_ENABLE */
#define PCI_DC_LOCK_CTL_HDS 0x1 /* HOLE DISABLE + PCI_ENABLE */
#define PCI_DC_LOCK_CTL_PDS 0x2 /* HOLE DISABLE + PCI DISABLE */
#define PCI_DC_LOCK_CTL_RES 0x3 /* RESERVED */
#define pciSetDC_LOCK(x) ( MMIO(DC_LOCK_CTL) = \
(MMIO(DC_LOCK_CTL) & ~PCI_DC_LOCK) | ((x & PCI_DC_LOCK_MASK) << PCI_DC_LOCK_SHIFT) )
#define pciExtractDC_LOCK() \
((MMIO(DC_LOCK_CTL) >> PCI_DC_LOCK_SHIFT) & PCI_DC_LOCK_MASK)
#define ALIGN(x,a) ( ( (x) + (a) -1 ) & ( ~ ( (a) - 1 ) ) )
#define PCI_IO_BUSY 0x04
#define PCI_IO_DONE 0x08
#define PCI_IO_READ 0x10
#define PCI_IO_WRITE 0x00
#define PCI_VENDORID_TM1 0x1131
#define PCI_DEVICEID_TM1 0x5400
#define PCI_VENDORID_SOUTHBRIDGE 0x10ad
#define PCI_DEVICEID_SOUTHBRIDGE 0x0565
#define PCI_VENDOR_ID_TM1S_IREF ( ( PCI_DEVICEID_TM1 << 16 ) | PCI_VENDORID_TM1 )
#define PCI_VENDOR_ID_SOUTH ( ( PCI_DEVICEID_SOUTHBRIDGE << 16 ) | PCI_VENDORID_SOUTHBRIDGE )
/* Configuration problems return code */
#define CONFIG_TIMEOUT 1000
#define CONFIG_BUSY_BIT 0x01
#define CONFIG_DONE_BIT 0x02
static int pciConfigStatus (UInt32 bits, UInt32 zero_flag);
static void pciDWORDAlignedCopy (
UInt8* Destination,
UInt8* Source,
UInt32 Length,
UInt32 AlignmentBase );
extern
tmLibdevErr_t
pciAddressFind (
unsigned id,
unsigned* CmdStatusAddrPointer )
{
unsigned cmd_status_addr;
unsigned cmd_status_val;
int i;
cmd_status_addr = (1 << 11);
for (i = 0; i < 21; i++)
{
pciConfigRead(cmd_status_addr, &cmd_status_val);
if (cmd_status_val == id)
{ /* found the board */
*CmdStatusAddrPointer = cmd_status_addr;
return TMLIBDEV_OK;
}
cmd_status_addr = cmd_status_addr << 1;
}
return PCI_ERR_ADDRESS_FIND;
}
extern
tmLibdevErr_t
pciConfigRead(
UInt32 address,
UInt32* data )
{
int err;
unsigned long config_data ;
/*Check for config busy*/
err = pciConfigStatus (CONFIG_BUSY_BIT, True);
if (err)
{
return PCI_ERR_CONFIG_READ ;
}
/*Execute the read*/
MMIO(CONFIG_ADR) = address ;
MMIO(CONFIG_CTL) = 0x10 ; /* read cycle, all bytes */
/* Wait for config done*/
err = pciConfigStatus (CONFIG_DONE_BIT, False);
if (err)
{
return PCI_ERR_CONFIG_READ ;
}
/*Get the data*/
config_data = MMIO(CONFIG_DATA) ;
/*Reset config done bit*/
MMIO(BIU_STATUS) = 0x2 ;
/*Check for config ! busy and ! done*/
err = pciConfigStatus (CONFIG_DONE_BIT | CONFIG_BUSY_BIT, True);
if (err)
{
return PCI_ERR_CONFIG_READ ;
}
*data = config_data;
return TMLIBDEV_OK;
}
extern
tmLibdevErr_t
pciConfigWrite(
UInt32 address,
UInt32 data)
{
int err;
/*Check for config busy*/
err = pciConfigStatus (CONFIG_BUSY_BIT, True);
if (err)
{
return PCI_ERR_CONFIG_WRITE;
}
/*Execute the write*/
MMIO(CONFIG_ADR) = address ;
MMIO(CONFIG_DATA) = data;
MMIO(CONFIG_CTL) = 0x00 ; /* write cycle, all bytes */
/*Wait for config done */
err = pciConfigStatus (CONFIG_DONE_BIT, False);
if (err)
{
return PCI_ERR_CONFIG_WRITE;
}
/*Reset config done bit*/
MMIO(BIU_STATUS) = 0x2 ;
/*Check for config ! busy and ! done*/
err = pciConfigStatus (CONFIG_DONE_BIT | CONFIG_BUSY_BIT, True);
if (err)
{
return PCI_ERR_CONFIG_WRITE;
}
return TMLIBDEV_OK;
}
extern
tmLibdevErr_t
pciMemoryReadUInt32 (
UInt32* Address,
UInt32* Data )
{
UInt32 GlobalInterruptState;
UInt32 DCLockCtlState;
GlobalInterruptState = intCLEAR_IEN();
DCLockCtlState = pciExtractDC_LOCK();
pciSetDC_LOCK(PCI_DC_LOCK_CTL_HDS);
*Data = *Address;
pciSetDC_LOCK(DCLockCtlState);
intRESTORE_IEN(GlobalInterruptState);
return TMLIBDEV_OK;
}
extern
tmLibdevErr_t
pciMemoryWriteUInt32 (
UInt32* Address,
UInt32 Data )
{
UInt32 GlobalInterruptState;
UInt32 DCLockCtlState;
GlobalInterruptState = intCLEAR_IEN();
DCLockCtlState = pciExtractDC_LOCK();
pciSetDC_LOCK(PCI_DC_LOCK_CTL_HDS);
*Address = Data;
pciSetDC_LOCK(DCLockCtlState);
intRESTORE_IEN(GlobalInterruptState);
return TMLIBDEV_OK;
}
extern
tmLibdevErr_t
pciMemoryReadUInt16 (
UInt16* Address,
UInt16* Data )
{
UInt32 GlobalInterruptState;
UInt32 DCLockCtlState;
GlobalInterruptState = intCLEAR_IEN();
DCLockCtlState = pciExtractDC_LOCK();
pciSetDC_LOCK(PCI_DC_LOCK_CTL_HDS);
*Data = *Address;
pciSetDC_LOCK(DCLockCtlState);
intRESTORE_IEN(GlobalInterruptState);
return TMLIBDEV_OK;
}
extern
tmLibdevErr_t
pciMemoryWriteUInt16 (
UInt16* Address,
UInt16 Data )
{
UInt32 GlobalInterruptState;
UInt32 DCLockCtlState;
GlobalInterruptState = intCLEAR_IEN();
DCLockCtlState = pciExtractDC_LOCK();
pciSetDC_LOCK(PCI_DC_LOCK_CTL_HDS);
*Address = Data;
pciSetDC_LOCK(DCLockCtlState);
intRESTORE_IEN(GlobalInterruptState);
return TMLIBDEV_OK;
}
extern
tmLibdevErr_t
pciMemoryReadUInt8 (
UInt8* Address,
UInt8* Data )
{
UInt32 GlobalInterruptState;
UInt32 DCLockCtlState;
GlobalInterruptState = intCLEAR_IEN();
DCLockCtlState = pciExtractDC_LOCK();
pciSetDC_LOCK(PCI_DC_LOCK_CTL_HDS);
*Data = *Address;
pciSetDC_LOCK(DCLockCtlState);
intRESTORE_IEN(GlobalInterruptState);
return TMLIBDEV_OK;
}
extern
tmLibdevErr_t
pciMemoryWriteUInt8 (
UInt8* Address, UInt8 Data )
{
UInt32 GlobalInterruptState;
UInt32 DCLockCtlState;
GlobalInterruptState = intCLEAR_IEN();
DCLockCtlState = pciExtractDC_LOCK();
pciSetDC_LOCK(PCI_DC_LOCK_CTL_HDS);
*Address = Data;
pciSetDC_LOCK(DCLockCtlState);
intRESTORE_IEN(GlobalInterruptState);
return TMLIBDEV_OK;
}
extern
tmLibdevErr_t
pciMemoryCopy(
UInt8 *Destination,
UInt8 *Source,
UInt32 Length )
{
UInt8 *SDRAMBegin, *SDRAMEnd;
UInt32 SDRAMPreAlignLength;
UInt8* SDRAMPreAlignAddress;
UInt32 SDRAMCacheAlignLength;
UInt8* SDRAMCacheAlignAddress;
UInt32 SDRAMPostAlignLength;
UInt8* SDRAMPostAlignAddress;
UInt8* PCIAddress;
dmaRequest_t DMARequest;
dmaDirection_t TransferDirection;
Int Instance;
tmLibdevErr_t ErrorCode;
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