l1main.c

TM1300/PNX1300系列DSP（主要用于视频处理）的自动boot程序

/*
 *  +-------------------------------------------------------------------+
 *  | Copyright (c) 1995,2000 TriMedia Technologies Inc.                |
 *  |                                                                   |
 *  | This software  is furnished under a license  and may only be used |
 *  | and copied in accordance with the terms  and conditions of such a |
 *  | license  and with  the inclusion of this  copyright notice.  This |
 *  | software or any other copies of this software may not be provided |
 *  | or otherwise  made available  to any other person.  The ownership |
 *  | and title of this software is not transferred.                    |
 *  |                                                                   |
 *  | The information  in this software  is subject  to change  without |
 *  | any  prior notice  and should not be construed as a commitment by |
 *  | TriMedia Technologies.                                            |
 *  |                                                                   |
 *  | This  code  and  information  is  provided  "as is"  without  any |
 *  | warranty of any kind,  either expressed or implied, including but |
 *  | not limited  to the implied warranties  of merchantability and/or |
 *  | fitness for any particular purpose.                               |
 *  +-------------------------------------------------------------------+
 *
 *  Module name              : l1main.c
 *
 *  Module type              : IMPLEMENTATION
 *
 *  Title                    : L1 boot code
 *
 *  Last update              : 15 July 1997
 *
 *  Description              :
 *
 *                             L1 boot code.
 *                             Copies L2 boot code from a PCI-slave UVEPROM
 */

#include <tm1/mmio.h>

/* downloader symbols                                   */
/* Patched when creating a memory image file using tmld */

extern          UInt32	_clock_freq_init[];
extern          UInt32	_begin_stack_init[];
extern volatile UInt32	_MMIO_base_init[];

/* MACROS  */

#define  CACHE_BL_SIZE            64

/* globals */

unsigned long    _clock_freq = (unsigned long)     _clock_freq_init;
volatile UInt32 *_MMIO_base  = (volatile UInt32 *) _MMIO_base_init;

custom_op void dcb(long, void *);
custom_op void iclr(void);

/*
 * copyback_dcache (unsigned addr, int nbytes)
 *   1. addr must be cache aligned.
 *      This function flushes nbytes starting at addr to memory.
 *
 * L1 boot code copies L2 boot code from some device
 * This needs to be flushed to memory before jumping to the
 * L2 load address
 */
static void
copyback_dcache(unsigned addr, int n)
{
  int i;

  for (i = 0; i < n; i = i + CACHE_BL_SIZE) {
    dcb(0, (void *)(addr + (unsigned)i));
  }
}

/*
 * iclr is in a separate function to ensure that it is in a
 * dtree by itself
 */
static void
clear_icache(void)
{
  iclr();
}

unsigned int
L1main()
{
  int i;
  unsigned char  byte;
  unsigned int  *base_addr = (unsigned int *)  L2_ROM_DEV_ADDR;
  unsigned char *load_addr = (unsigned char *) L2_LOAD_ADDR;

  /* Load L2 code from an attached PCI device  */

  /* start copying of L2 code to sdram */
  /* Assumes TM1 debug board schematics.
   * Assumes L2 boot program is in a single UVEPROM plugged into
   * byte 3 slot. The other 3 slots (which supply bytes 0, 1, and 2
   * of a word loaded from PCI) are empty.
   *
   */

  for (i=0; i < L2_CODE_SIZE; i++) {
#ifdef __BIG_ENDIAN__
    byte = base_addr[i] & 0xFF;
#else
    byte = (base_addr[i] >> 24) & 0xFF;
#endif
    load_addr[i] = byte;
  }

  /* flush data cache */
  copyback_dcache(L2_LOAD_ADDR, L2_CODE_SIZE);

  /* clear any interrupts */
  MMIO(ICLEAR)= 0xffffffff;

  clear_icache();

  /*
   * Return from L1main() causes L2 code to be executed.
   */

  return L2_LOAD_ADDR;
}