📄 dec21140.h
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/***********************************************************************/
/* */
/* MODULE: net/dec21140.h */
/* DATE: 98/06/08 */
/* PURPOSE: Contains definitions for Ethernet Controller */
/* */
/*---------------------------------------------------------------------*/
/* */
/* Copyright 1991-1997, Integrated Systems, Inc. */
/* ALL RIGHTS RESERVED */
/* */
/* Permission is hereby granted to licensees of Integrated Systems, */
/* Inc. products to use or abstract this computer program for the */
/* sole purpose of implementing a product based on Integrated */
/* Systems, Inc. products. No other rights to reproduce, use, */
/* or disseminate this computer program, whether in part or in */
/* whole, are granted. */
/* */
/* Integrated Systems, Inc. makes no representation or warranties */
/* with respect to the performance of this computer program, and */
/* specifically disclaims any responsibility for any damages, */
/* special or consequential, connected with the use of this program. */
/* */
/***********************************************************************/
#ifndef _DEC21140_H
#define _DEC21140_H
#include "bsp.h"
#include <pna.h>
#include <bspfuncs.h>
#include <pna_mib.h>
#include <psos.h>
#include <stdio.h>
/***********************************************************************/
/* Symbol Definitions */
/***********************************************************************/
/*
** Configuration Register Address Offsets
*/
#define CFID 0x00
#define CFCS 0x04
#define CF_CMD 0x04
#define CF_STATUS 0x06
#define CFRV 0x08
#define CFLT 0x0C
#define CF_LINE_SZ 0x0C
#define CF_LATENCY 0x0D
#define CBIO 0x10
#define CBMA 0x14
#define SSID 0x2C
#define CBER 0x30
#define CFIT 0x3C
#define CF_DRIVER 0x41
/*---------------------------------------------------------------------*/
/* PCI address of the chip's Control and Status Registers */
/*---------------------------------------------------------------------*/
#define LAN_PCI_IO_BASE 0x02000000
/*---------------------------------------------------------------------*/
/*---------------------------------------------------------------------*/
#define V_LAN intINT_0
/***********************************************************************/
/* General Definitions */
/***********************************************************************/
#define UCHAR unsigned char
#define USHORT unsigned short
#define ULONG unsigned long
#define REG8(addr) *((volatile UCHAR *) addr)
#define REG16(addr) *((volatile USHORT *) addr)
#define REG32(addr) *((volatile ULONG *) addr)
/*---------------------------------------------------------------------*/
/* LAN configuration structure fields */
/* - Bit definitions */
/* - Masks */
/* - Default Values */
/*---------------------------------------------------------------------*/
#define LAN_VENDOR_ID 0x1011 /* Vendor Id for manufacture */
#define DEC_21140_ID 0x0009 /* Device Id for DEC21140 */
#define DEC_21040_ID 0x0002 /* Device Id for DEC21040 */
#define LAN_DEVICE_ID DEC_21140_ID /* Device Id for Gen 2 */
/*---------------------------------------------------------------------*/
/* Command Register */
/*---------------------------------------------------------------------*/
#define LAN_COM_SERR 0x0080 /* Signal Error Enable */
#define LAN_COM_PER 0x0040 /* Parity Error Enable */
#define LAN_COM_SCE 0x0008 /* Special Cycle Enable */
#define LAN_COM_BME 0x0004 /* Bus Master Enable */
#define LAN_COM_MSE 0x0002 /* Memory Space Enable */
#define LAN_COM_IOSE 0x0001 /* IO Space Enable */
/*---------------------------------------------------------------------*/
/* Device Status Register */
/*---------------------------------------------------------------------*/
#define LAN_DS_PER 0x8000 /* Parity error detected */
#define LAN_DS_SERR 0x4000 /* SERR# Status */
#define LAN_DS_MA 0x2000 /* Master-Abort Status */
#define LAN_DS_RTA 0x1000 /* Received Target-Abort */
#define LAN_DS_STA 0x0800 /* Signaled Target-Abort */
#define LAN_DS_DEVT 0x0600 /* LAN DEVSEL# Timing Status */
#define LAN_DS_DPAR 0x0100 /* Data Parity Report */
#define LAN_DS_FB2B 0x0080 /* Fast Back to Back capable */
/*---------------------------------------------------------------------*/
/* Base Class */
/*---------------------------------------------------------------------*/
#define LAN_BASE_CLS 0x02 /* Base Class - Network Cntlr */
/*---------------------------------------------------------------------*/
/* Sub Class Register */
/*---------------------------------------------------------------------*/
#define LAN_SUB_CLASS 0x00 /* Sub Class - Network Cntlr */
/*---------------------------------------------------------------------*/
/* Revision Identification Register */
/*---------------------------------------------------------------------*/
#define LAN_RID_VALID 0xFF /* Valid revision bits */
#define LAN_STEP_02 0x20 /* Step number */
#define LAN_RID_00 0x00 /* Revision 00 */
#define LAN_RID_01 0x01 /* Revision 01 */
#define LAN_RID_02 0x02 /* Revision 02 */
#define LAN_RID_03 0x03 /* Revision 03 */
/*---------------------------------------------------------------------*/
/* Latency Timer Register - generic PCI layout */
/*---------------------------------------------------------------------*/
#define LAN_LAT_MASK 0xFF /* Valid Latency Timer Bits */
/*---------------------------------------------------------------------*/
/* IO Map Base Address Register */
/*---------------------------------------------------------------------*/
#define LAN_IOMAP_BASE 0xFFFFFF80 /* Valid IO Address Bits */
#define LAN_IOMAP_FLAG 0x00000001 /* IO Space Map Indicator */
/*---------------------------------------------------------------------*/
/* Memory Map Base Address Register */
/*---------------------------------------------------------------------*/
#define LAN_MEMMAP_BASE 0xFFFFFF80 /* Valid Memory Address Bits */
#define LAN_MEMMAP_FLAG 0x00000001 /* Memory Space Map Indicator */
/*---------------------------------------------------------------------*/
/* Interrupt Pin Register */
/*---------------------------------------------------------------------*/
#define LAN_IPIN_INTA 0x01 /* INTA# Pin used */
#define LAN_ILIN_ROUT 0xFF /* Interrupt Routing Register */
/*---------------------------------------------------------------------*/
/* 21140A Control and Status registers */
/*---------------------------------------------------------------------*/
#define CSR0 (LAN_PCI_IO_BASE + 0x00)
#define CSR1 (LAN_PCI_IO_BASE + 0x08)
#define CSR2 (LAN_PCI_IO_BASE + 0x10)
#define CSR3 (LAN_PCI_IO_BASE + 0x18)
#define CSR4 (LAN_PCI_IO_BASE + 0x20)
#define CSR5 (LAN_PCI_IO_BASE + 0x28)
#define CSR6 (LAN_PCI_IO_BASE + 0x30)
#define CSR7 (LAN_PCI_IO_BASE + 0x38)
#define CSR8 (LAN_PCI_IO_BASE + 0x40)
#define CSR9 (LAN_PCI_IO_BASE + 0x48)
#define CSR10 (LAN_PCI_IO_BASE + 0x50)
#define CSR11 (LAN_PCI_IO_BASE + 0x58)
#define CSR12 (LAN_PCI_IO_BASE + 0x60)
#define CSR13 (LAN_PCI_IO_BASE + 0x68)
#define CSR14 (LAN_PCI_IO_BASE + 0x70)
#define CSR15 (LAN_PCI_IO_BASE + 0x78)
/*---------------------------------------------------------------------*/
/* Lan chip non configuration structure fields */
/* - Bit definitions */
/* - Masks */
/* - Default Values */
/*---------------------------------------------------------------------*/
/* Control & Status Register 0 - Bus Mode Regsiter */
/*---------------------------------------------------------------------*/
#define LAN_CSR0_SWR (1 << 0) /* Software Reset */
#define LAN_CSR0_BAR 0x00000002 /* Bus Arbitration */
#define LAN_CSR0_DSL 0x0000007C /* Descriptor Skip Length */
#define LAN_CSR0_BLE 0x00000080 /* 1:Big or 0:Little Endian */
#define LAN_CSR0_PBL 0x00003F00 /* Programmable Burst Length */
#define LAN_CSR0_PBL00 0x00000000 /* Programmable Burst Length = 0*/
#define LAN_CSR0_PBL01 0x00000100 /* Programmable Burst Length = 1*/
#define LAN_CSR0_PBL02 0x00000200 /* Programmable Burst Length = 2*/
#define LAN_CSR0_PBL04 0x00000400 /* Programmable Burst Length = 4*/
#define LAN_CSR0_PBL08 0x00000800 /* Programmable Burst Length = 8*/
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