_primary.vhd

来自「基于spi协议的串口实现」· VHDL 代码 · 共 26 行

library verilog;
use verilog.vl_types.all;
entity spi_top is
    generic(
        max1            : integer := 8;
        max2            : integer := 8;
        st0             : integer := 0;
        st1             : integer := 1;
        st2             : integer := 2;
        st3             : integer := 3
    );
    port(
        clk             : out    vl_logic;
        mosi            : out    vl_logic;
        miso            : in     vl_logic;
        en              : out    vl_logic;
        rreq            : out    vl_logic;
        wreq            : out    vl_logic;
        data_bus_in     : in     vl_logic_vector(7 downto 0);
        data_bus_out    : out    vl_logic_vector(7 downto 0);
        ack             : in     vl_logic;
        flag            : in     vl_logic_vector(7 downto 0);
        test_clk        : in     vl_logic
    );
end spi_top;