_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity count_sub_reg is
    generic(
        width           : integer := 6;
        a_width         : integer := 6;
        b_width         : integer := 6;
        q_width         : integer := 2;
        c_enable_rlocs  : integer := 1;
        no              : integer := 0;
        yes             : integer := 1;
        zero            : integer := 0
    );
    port(
        a_in            : in     vl_logic_vector;
        b_in            : in     vl_logic_vector;
        clk             : in     vl_logic;
        rst_a           : in     vl_logic;
        rst_b           : in     vl_logic;
        q_out           : out    vl_logic_vector
    );
end count_sub_reg;