_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity c_bit_correlator_v3_0 is
    generic(
        c_channels      : integer := 1;
        c_data_width    : integer := 1;
        c_enable_rlocs  : integer := 0;
        c_has_mask      : integer := 0;
        c_has_sel_indicator: integer := 0;
        c_input_type    : integer := 0;
        c_latency       : integer := 2;
        c_mem_init_file : string  := "bit_corr_16.mif";
        c_reload        : integer := 0;
        c_reload_delay  : integer := 0;
        c_reload_mem_type: integer := 0;
        c_shape         : integer := 0;
        c_taps          : integer := 16
    );
    port(
        clk             : in     vl_logic;
        din             : in     vl_logic_vector;
        ld_din          : in     vl_logic;
        ld_we           : in     vl_logic;
        coef_ld         : in     vl_logic;
        nd              : in     vl_logic;
        dout            : out    vl_logic_vector;
        rdy             : out    vl_logic;
        rfd             : out    vl_logic;
        sel_i           : out    vl_logic_vector;
        sel_o           : out    vl_logic_vector
    );
end c_bit_correlator_v3_0;