_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity dither_add_v4_0 is
    generic(
        accum_width     : integer := 16;
        c_has_aclr      : integer := 0;
        c_has_ce        : integer := 0;
        c_has_sclr      : integer := 0;
        c_pipelined     : integer := 0;
        phase_width     : integer := 8
    );
    port(
        a               : in     vl_logic_vector;
        aclr            : in     vl_logic;
        ce              : in     vl_logic;
        clk             : in     vl_logic;
        dithered_phase  : out    vl_logic_vector;
        nd              : in     vl_logic;
        rdy             : out    vl_logic;
        sclr            : in     vl_logic
    );
end dither_add_v4_0;