_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity vfft32_v2_0 is
    generic(
        butterfly_precision: integer := 16;
        c_family_int    : integer := 0;
        data_memory     : string  := "";
        memory_architecture: integer := 3;
        mult_type       : integer := 0;
        phase_factor_precision: integer := 16;
        scaling_schedule_mem1: string  := "";
        scaling_schedule_mem2: string  := ""
    );
    port(
        clk             : in     vl_logic;
        ce              : in     vl_logic;
        reset           : in     vl_logic;
        start           : in     vl_logic;
        fwd_inv         : in     vl_logic;
        mrd             : in     vl_logic;
        mwr             : in     vl_logic;
        xn_re           : in     vl_logic_vector;
        xn_im           : in     vl_logic_vector;
        ovflo           : out    vl_logic;
        done            : out    vl_logic;
        edone           : out    vl_logic;
        io              : out    vl_logic;
        eio             : out    vl_logic;
        busy            : out    vl_logic;
        xk_re           : out    vl_logic_vector;
        xk_im           : out    vl_logic_vector
    );
end vfft32_v2_0;