_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity sid_bhv_forney_array is
    generic(
        c_branch_length_constant: integer := 1;
        c_branch_length_file: string  := "null.mif";
        c_branch_length_type: integer := 0;
        c_enable_rlocs  : integer := 0;
        c_has_aclr      : integer := 1;
        c_has_ce        : integer := 0;
        c_has_fdo       : integer := 0;
        c_has_ndo       : integer := 0;
        c_has_rdy       : integer := 0;
        c_has_rfd       : integer := 0;
        c_has_rffd      : integer := 0;
        c_has_sclr      : integer := 1;
        c_memstyle      : integer := 0;
        c_mode          : integer := 0;
        c_num_branches  : integer := 2;
        c_pipe_level    : integer := 0;
        c_symbol_width  : integer := 8;
        iiiil00oii0lool0010l1ooloi: integer := 1
    );
    port(
        clk             : in     vl_logic;
        din             : in     vl_logic_vector;
        nd              : in     vl_logic;
        fd              : in     vl_logic;
        ce              : in     vl_logic;
        sclr            : in     vl_logic;
        aclr            : in     vl_logic;
        dout            : out    vl_logic_vector;
        rdy             : out    vl_logic;
        rffd            : out    vl_logic;
        rfd             : out    vl_logic;
        fdo             : out    vl_logic;
        ndo             : out    vl_logic
    );
end sid_bhv_forney_array;