_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity vfft32_addr_gen_v2_0 is
    generic(
        points_power    : integer := 5;
        memory_architecture: integer := 1;
        ainit_val       : string  := "00000";
        rank_ctr_ainit_val: string  := "00";
        thirty_one      : string  := "11111";
        rank_counter_width: integer := 2;
        three           : string  := "11";
        one_string      : string  := "00001";
        one_string_1    : string  := "01";
        two             : string  := "10";
        ascii_zero      : integer := 48
    );
    port(
        clk             : in     vl_logic;
        ce              : in     vl_logic;
        reset           : in     vl_logic;
        start           : in     vl_logic;
        io_pulse        : in     vl_logic;
        delayed_io_pulse_out: out    vl_logic;
        address         : out    vl_logic_vector;
        rank_number     : out    vl_logic_vector(1 downto 0)
    );
end vfft32_addr_gen_v2_0;