_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity c_gate_bus_v1_0 is
    generic(
        c_ainit_val     : string  := "";
        c_enable_rlocs  : integer := 1;
        c_gate_type     : integer := 0;
        c_has_aclr      : integer := 0;
        c_has_ainit     : integer := 0;
        c_has_aset      : integer := 0;
        c_has_ce        : integer := 0;
        c_has_o         : integer := 0;
        c_has_q         : integer := 1;
        c_has_sclr      : integer := 0;
        c_has_sinit     : integer := 0;
        c_has_sset      : integer := 0;
        c_inputs        : integer := 2;
        c_input_a_inv_mask: string  := "";
        c_input_b_inv_mask: string  := "";
        c_input_c_inv_mask: string  := "";
        c_input_d_inv_mask: string  := "";
        c_sinit_val     : string  := "";
        c_sync_enable   : integer := 0;
        c_sync_priority : integer := 1;
        c_width         : integer := 16
    );
    port(
        ia              : in     vl_logic_vector;
        ib              : in     vl_logic_vector;
        ic              : in     vl_logic_vector;
        id              : in     vl_logic_vector;
        clk             : in     vl_logic;
        ce              : in     vl_logic;
        aclr            : in     vl_logic;
        aset            : in     vl_logic;
        ainit           : in     vl_logic;
        sclr            : in     vl_logic;
        sset            : in     vl_logic;
        sinit           : in     vl_logic;
        o               : out    vl_logic_vector;
        q               : out    vl_logic_vector
    );
end c_gate_bus_v1_0;