_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity dividervht is
    generic(
        divclk_sel      : integer := 1;
        dividend_width  : integer := 8;
        divisor_width   : integer := 8;
        fractional_b    : integer := 0;
        fractional_width: integer := 8;
        signed_b        : integer := 0
    );
    port(
        dividend        : in     vl_logic_vector;
        divisor         : in     vl_logic_vector;
        quot            : out    vl_logic_vector;
        remd            : out    vl_logic_vector;
        c               : in     vl_logic
    );
end dividervht;