_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity vfft32_delay_wrapper_v2_0 is
    generic(
        addr_width      : integer := 4;
        depth           : integer := 12;
        data_width      : integer := 16;
        ainit_val       : integer := 48;
        sinit_val       : integer := 48;
        zero            : integer := 0
    );
    port(
        addr            : in     vl_logic_vector;
        data            : in     vl_logic_vector;
        clk             : in     vl_logic;
        start           : in     vl_logic;
        reset           : in     vl_logic;
        delayed_data    : out    vl_logic_vector
    );
end vfft32_delay_wrapper_v2_0;