_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity vfft32_bfly_buf_fft_v2_0 is
    generic(
        b               : integer := 12;
        w_width         : integer := 12;
        memory_configuration: integer := 3;
        mem_init_file   : string  := "000000";
        mem_init_file_2 : string  := "000000";
        butterfly_latency: integer := 6;
        start_to_bfly_input_latency: integer := 3;
        bfly_res_avail_latency: integer := 17;
        bfly_scale_delay_by: integer := 16;
        init_value      : string  := "00000";
        count_by_value  : string  := "0000001";
        thresh_0_value  : string  := "0000000";
        five            : string  := "101";
        ascii_zero      : integer := 48;
        string_zero_7   : string  := "0000000"
    );
    port(
        clk             : in     vl_logic;
        ce              : in     vl_logic;
        start           : in     vl_logic;
        reset           : in     vl_logic;
        conj            : in     vl_logic;
        fwd_inv         : in     vl_logic;
        rank_number     : in     vl_logic_vector(1 downto 0);
        dr              : in     vl_logic_vector;
        di              : in     vl_logic_vector;
        xkr             : out    vl_logic_vector;
        xki             : out    vl_logic_vector;
        wr              : in     vl_logic_vector;
        wi              : in     vl_logic_vector;
        done            : in     vl_logic;
        e_result_avail  : out    vl_logic;
        e_result_ready  : out    vl_logic;
        result_avail    : out    vl_logic;
        bfly_res_avail  : out    vl_logic;
        e_bfly_res_avail: out    vl_logic;
        ce_phase_factors: out    vl_logic;
        ovflo           : out    vl_logic;
        y0r             : out    vl_logic_vector;
        y0i             : out    vl_logic_vector;
        y1r             : out    vl_logic_vector;
        y1i             : out    vl_logic_vector;
        y2r             : out    vl_logic_vector;
        y2i             : out    vl_logic_vector;
        y3r             : out    vl_logic_vector;
        y3i             : out    vl_logic_vector
    );
end vfft32_bfly_buf_fft_v2_0;