_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity fifoctlr_ns_v4 is
    generic(
        width           : integer := 6;
        wr_width        : integer := 6;
        rd_width        : integer := 6;
        c_enable_rlocs  : integer := 1;
        c_has_almost_full: integer := 1;
        c_has_almost_empty: integer := 1;
        c_has_wrsync_dcount: integer := 1;
        wrsync_dcount_width: integer := 6;
        c_has_rdsync_dcount: integer := 1;
        rdsync_dcount_width: integer := 6;
        c_has_rd_ack    : integer := 1;
        c_rd_ack_low    : integer := 0;
        c_has_rd_error  : integer := 1;
        c_rd_error_low  : integer := 0;
        c_has_wr_ack    : integer := 1;
        c_wr_ack_low    : integer := 0;
        c_has_wr_error  : integer := 1;
        c_wr_error_low  : integer := 0;
        no              : integer := 0;
        yes             : integer := 1;
        ascii_zero      : integer := 48;
        ascii_one       : integer := 49
    );
    port(
        fifo_reset_in   : in     vl_logic;
        read_clock_in   : in     vl_logic;
        write_clock_in  : in     vl_logic;
        read_request_in : in     vl_logic;
        write_request_in: in     vl_logic;
        read_enable_out : out    vl_logic;
        write_enable_out: out    vl_logic;
        full_flag_out   : out    vl_logic;
        empty_flag_out  : out    vl_logic;
        almost_full_out : out    vl_logic;
        almost_empty_out: out    vl_logic;
        read_addr_out   : out    vl_logic_vector;
        write_addr_out  : out    vl_logic_vector;
        wrsync_count_out: out    vl_logic_vector;
        rdsync_count_out: out    vl_logic_vector;
        read_ack        : out    vl_logic;
        read_error      : out    vl_logic;
        write_ack       : out    vl_logic;
        write_error     : out    vl_logic
    );
end fifoctlr_ns_v4;