_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity cam_v2_0 is
    generic(
        c_addr_type     : integer := 1;
        c_depth         : integer := 16;
        c_enable_rlocs  : integer := 0;
        c_has_addr_valid: integer := 0;
        c_has_cmp_din   : integer := 0;
        c_has_data_mask : integer := 0;
        c_has_en        : integer := 0;
        c_has_match_rst : integer := 0;
        c_match_addr_width: integer := 16;
        c_mem_type      : integer := 0;
        c_ternary_mode  : integer := 0;
        c_width         : integer := 1;
        srl_size        : integer := 16
    );
    port(
        clk             : in     vl_logic;
        din             : in     vl_logic_vector;
        en              : in     vl_logic;
        we              : in     vl_logic;
        cmp_din         : in     vl_logic_vector;
        wr_addr         : in     vl_logic_vector;
        match           : out    vl_logic;
        match_addr      : out    vl_logic_vector;
        busy            : out    vl_logic
    );
end cam_v2_0;