_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity async_fifo_v1_0 is
    generic(
        c_data_width    : integer := 8;
        c_enable_rlocs  : integer := 0;
        c_fifo_depth    : integer := 511;
        c_has_almost_empty: integer := 1;
        c_has_almost_full: integer := 1;
        c_has_rd_ack    : integer := 1;
        c_has_rd_count  : integer := 1;
        c_has_rd_err    : integer := 1;
        c_has_wr_ack    : integer := 1;
        c_has_wr_count  : integer := 1;
        c_has_wr_err    : integer := 1;
        c_rd_ack_low    : integer := 0;
        c_rd_count_width: integer := 6;
        c_rd_err_low    : integer := 0;
        c_use_blockmem  : integer := 1;
        c_wr_ack_low    : integer := 0;
        c_wr_count_width: integer := 6;
        c_wr_err_low    : integer := 0
    );
    port(
        din             : in     vl_logic_vector;
        wr_en           : in     vl_logic;
        wr_clk          : in     vl_logic;
        rd_en           : in     vl_logic;
        rd_clk          : in     vl_logic;
        ainit           : in     vl_logic;
        dout            : out    vl_logic_vector;
        full            : out    vl_logic;
        empty           : out    vl_logic;
        almost_full     : out    vl_logic;
        almost_empty    : out    vl_logic;
        wr_count        : out    vl_logic_vector;
        rd_count        : out    vl_logic_vector;
        rd_ack          : out    vl_logic;
        rd_err          : out    vl_logic;
        wr_ack          : out    vl_logic;
        wr_err          : out    vl_logic
    );
end async_fifo_v1_0;