_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity vfft32_phase_factor_adgen_v2_0 is
    generic(
        w_width         : integer := 16;
        ainit_val       : string  := "0000";
        sinit_val       : string  := "0000";
        fifteen         : string  := "1111";
        sixteen_string  : string  := "10000";
        zero_string     : string  := "00000"
    );
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        start           : in     vl_logic;
        ce              : in     vl_logic;
        fwd_inv         : in     vl_logic;
        rank_number     : in     vl_logic_vector(1 downto 0);
        w_addr_sine     : out    vl_logic_vector(4 downto 0);
        w_addr_cos      : out    vl_logic_vector(3 downto 0)
    );
end vfft32_phase_factor_adgen_v2_0;