_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity vfft32_result_memory_v2_0 is
    generic(
        result_width    : integer := 12;
        points_power    : integer := 5;
        data_memory     : string  := "";
        memory_architecture: integer := 3;
        zero_data       : integer := 0;
        one_string      : integer := 1;
        three           : integer := 3;
        ainit_val       : integer := 0;
        sinit_val       : integer := 0;
        one_string_1    : integer := 1;
        thirty_one      : integer := 31;
        ainit_val_1     : integer := 0;
        sinit_val_1     : integer := 0
    );
    port(
        clk             : in     vl_logic;
        ce              : in     vl_logic;
        reset           : in     vl_logic;
        mrd             : in     vl_logic;
        fwd_inv         : in     vl_logic;
        y0r             : in     vl_logic_vector;
        y0i             : in     vl_logic_vector;
        y1r             : in     vl_logic_vector;
        y1i             : in     vl_logic_vector;
        y2r             : in     vl_logic_vector;
        y2i             : in     vl_logic_vector;
        y3r             : in     vl_logic_vector;
        y3i             : in     vl_logic_vector;
        e_result_avail  : in     vl_logic;
        e_result_ready  : in     vl_logic;
        reset_io        : in     vl_logic;
        eio_out         : in     vl_logic;
        result_ready    : out    vl_logic;
        xk_result_re    : out    vl_logic_vector;
        xk_result_im    : out    vl_logic_vector
    );
end vfft32_result_memory_v2_0;