_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity reg_ainit_v2 is
    generic(
        reg_size        : integer := 6;
        init_val        : string  := "000000";
        c_enable_rlocs  : integer := 1;
        no              : integer := 0;
        yes             : integer := 1
    );
    port(
        rst             : in     vl_logic;
        clk             : in     vl_logic;
        cen             : in     vl_logic;
        din             : in     vl_logic_vector;
        qout            : out    vl_logic_vector
    );
end reg_ainit_v2;