_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity sdafirvht is
    generic(
        antisymmetry    : integer := 0;
        cascade         : integer := 0;
        coefdata0       : integer := 1;
        coefdata1       : integer := 1;
        coefdata10      : integer := 1;
        coefdata11      : integer := 1;
        coefdata12      : integer := 1;
        coefdata13      : integer := 1;
        coefdata14      : integer := 1;
        coefdata15      : integer := 1;
        coefdata16      : integer := 1;
        coefdata17      : integer := 1;
        coefdata18      : integer := 1;
        coefdata19      : integer := 1;
        coefdata2       : integer := 1;
        coefdata20      : integer := 1;
        coefdata21      : integer := 1;
        coefdata22      : integer := 1;
        coefdata23      : integer := 1;
        coefdata24      : integer := 1;
        coefdata25      : integer := 1;
        coefdata26      : integer := 1;
        coefdata27      : integer := 1;
        coefdata28      : integer := 1;
        coefdata29      : integer := 1;
        coefdata3       : integer := 1;
        coefdata30      : integer := 1;
        coefdata31      : integer := 1;
        coefdata32      : integer := 1;
        coefdata33      : integer := 1;
        coefdata34      : integer := 1;
        coefdata35      : integer := 1;
        coefdata36      : integer := 1;
        coefdata37      : integer := 1;
        coefdata38      : integer := 1;
        coefdata39      : integer := 1;
        coefdata4       : integer := 1;
        coefdata5       : integer := 1;
        coefdata6       : integer := 1;
        coefdata7       : integer := 1;
        coefdata8       : integer := 1;
        coefdata9       : integer := 1;
        coef_width      : integer := 8;
        input_width     : integer := 8;
        number_of_taps  : integer := 8;
        output_width    : integer := 8;
        short_wide_floorplan: integer := 1;
        signed_input_data: integer := 1;
        symmetry        : integer := 1;
        trim_empty_roms : integer := 1;
        full_result_width: integer := 64;
        worst_case_latency: integer := 6
    );
    port(
        data            : in     vl_logic_vector;
        nd              : in     vl_logic;
        rfd             : out    vl_logic;
        sinf            : in     vl_logic;
        sinr            : in     vl_logic;
        soutf           : out    vl_logic;
        soutr           : out    vl_logic;
        ck              : in     vl_logic;
        rslt            : out    vl_logic_vector;
        rdy             : out    vl_logic
    );
end sdafirvht;