_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity pscvht is
    generic(
        create_rpm      : integer := 0;
        port_width      : integer := 8
    );
    port(
        pi              : in     vl_logic_vector;
        sdi             : in     vl_logic;
        l               : in     vl_logic;
        c               : in     vl_logic;
        ce              : in     vl_logic;
        sdo             : out    vl_logic;
        po              : out    vl_logic_vector
    );
end pscvht;