_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity c_addsub_v2_0 is
    generic(
        c_add_mode      : integer := 0;
        c_ainit_val     : string  := "";
        c_a_type        : integer := 1;
        c_a_width       : integer := 16;
        c_bypass_enable : integer := 0;
        c_bypass_low    : integer := 0;
        c_b_constant    : integer := 0;
        c_b_type        : integer := 1;
        c_b_value       : string  := "";
        c_b_width       : integer := 16;
        c_enable_rlocs  : integer := 1;
        c_has_aclr      : integer := 0;
        c_has_add       : integer := 0;
        c_has_ainit     : integer := 0;
        c_has_aset      : integer := 0;
        c_has_a_signed  : integer := 0;
        c_has_bypass    : integer := 0;
        c_has_b_in      : integer := 1;
        c_has_b_out     : integer := 0;
        c_has_b_signed  : integer := 0;
        c_has_ce        : integer := 0;
        c_has_c_in      : integer := 1;
        c_has_c_out     : integer := 0;
        c_has_ovfl      : integer := 0;
        c_has_q         : integer := 1;
        c_has_q_b_out   : integer := 0;
        c_has_q_c_out   : integer := 0;
        c_has_q_ovfl    : integer := 0;
        c_has_s         : integer := 0;
        c_has_sclr      : integer := 0;
        c_has_sinit     : integer := 0;
        c_has_sset      : integer := 0;
        c_high_bit      : integer := 15;
        c_low_bit       : integer := 0;
        c_out_width     : integer := 16;
        c_pipe_stages   : integer := 1;
        c_sinit_val     : string  := "";
        c_sync_enable   : integer := 0;
        c_sync_priority : integer := 1
    );
    port(
        a               : in     vl_logic_vector;
        b               : in     vl_logic_vector;
        clk             : in     vl_logic;
        add             : in     vl_logic;
        c_in            : in     vl_logic;
        b_in            : in     vl_logic;
        ce              : in     vl_logic;
        bypass          : in     vl_logic;
        aclr            : in     vl_logic;
        aset            : in     vl_logic;
        ainit           : in     vl_logic;
        sclr            : in     vl_logic;
        sset            : in     vl_logic;
        sinit           : in     vl_logic;
        a_signed        : in     vl_logic;
        b_signed        : in     vl_logic;
        ovfl            : out    vl_logic;
        c_out           : out    vl_logic;
        b_out           : out    vl_logic;
        q_ovfl          : out    vl_logic;
        q_c_out         : out    vl_logic;
        q_b_out         : out    vl_logic;
        s               : out    vl_logic_vector;
        q               : out    vl_logic_vector
    );
end c_addsub_v2_0;