_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity c_cic_v2_0 is
    generic(
        c_data_width    : integer := 10;
        c_differential_delay: integer := 1;
        c_enable_rlocs  : integer := 0;
        c_filter_type   : integer := 1;
        c_result_width  : integer := 12;
        c_sample_rate_change: integer := 8;
        c_stages        : integer := 1;
        accum_max_width : integer := 64
    );
    port(
        din             : in     vl_logic_vector;
        nd              : in     vl_logic;
        clk             : in     vl_logic;
        rfd             : out    vl_logic;
        rdy             : out    vl_logic;
        dout            : out    vl_logic_vector
    );
end c_cic_v2_0;