_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity rs_decoder_v2_0 is
    generic(
        c_clks_per_sym  : integer := 1;
        c_family_int    : integer := 0;
        c_gen_start     : integer := 0;
        c_h             : integer := 1;
        c_has_ce        : integer := 0;
        c_has_data_del  : integer := 0;
        c_has_erase     : integer := 0;
        c_has_sr        : integer := 0;
        c_huset         : string  := "MOD";
        c_k             : integer := 188;
        c_memstyle      : integer := 2;
        c_n             : integer := 204;
        c_polynomial    : integer := 0;
        c_spec          : integer := 0;
        c_symbol_width  : integer := 8;
        c_sync_mode     : integer := 0;
        c_usehuset      : integer := 1;
        c_userpm        : integer := 1;
        iil0ii0o0lii0llllil1lo1o0i: integer := 1;
        iooli0l1lio1lloil00llil101: integer := 12
    );
    port(
        data_in         : in     vl_logic_vector;
        sync            : in     vl_logic;
        clk             : in     vl_logic;
        ce              : in     vl_logic;
        erase           : in     vl_logic;
        reset           : in     vl_logic;
        sr              : in     vl_logic;
        err_cnt         : out    vl_logic_vector;
        err_found       : out    vl_logic;
        fail            : out    vl_logic;
        blk_strt        : out    vl_logic;
        blk_end         : out    vl_logic;
        erase_cnt       : out    vl_logic_vector;
        ready           : out    vl_logic;
        data_out        : out    vl_logic_vector;
        data_del        : out    vl_logic_vector
    );
end rs_decoder_v2_0;