_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity sync_fifo_v1_0 is
    generic(
        c_dcount_width  : integer := 9;
        c_enable_rlocs  : integer := 0;
        c_has_dcount    : integer := 1;
        c_has_rd_ack    : integer := 1;
        c_has_rd_err    : integer := 1;
        c_has_wr_ack    : integer := 1;
        c_has_wr_err    : integer := 1;
        c_memory_type   : integer := 0;
        c_ports_differ  : integer := 0;
        c_rd_ack_low    : integer := 0;
        c_rd_err_low    : integer := 0;
        c_read_data_width: integer := 16;
        c_read_depth    : integer := 0;
        c_write_data_width: integer := 16;
        c_write_depth   : integer := 16;
        c_wr_ack_low    : integer := 1;
        c_wr_err_low    : integer := 1
    );
    port(
        clk             : in     vl_logic;
        sinit           : in     vl_logic;
        din             : in     vl_logic_vector;
        wr_en           : in     vl_logic;
        rd_en           : in     vl_logic;
        dout            : out    vl_logic_vector;
        full            : out    vl_logic;
        empty           : out    vl_logic;
        rd_ack          : out    vl_logic;
        wr_ack          : out    vl_logic;
        rd_err          : out    vl_logic;
        wr_err          : out    vl_logic;
        data_count      : out    vl_logic_vector
    );
end sync_fifo_v1_0;