_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity ncoiqvht is
    generic(
        acc_width       : integer := 8;
        amp_width       : integer := 6;
        inc_width       : integer := 4;
        phase_width     : integer := 4
    );
    port(
        phase_inc       : in     vl_logic_vector;
        load            : in     vl_logic;
        c               : in     vl_logic;
        clr             : in     vl_logic;
        ampi            : out    vl_logic_vector;
        ampq            : out    vl_logic_vector
    );
end ncoiqvht;