_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity vfft32_working_memory_v2_0 is
    generic(
        b               : integer := 12;
        points_power    : integer := 5;
        memory_architecture: integer := 3;
        data_memory     : string  := "";
        bfly_res_avail_latency: integer := 16
    );
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        start           : in     vl_logic;
        xbar_y          : in     vl_logic;
        ext_to_xbar_y_temp_out: in     vl_logic_vector(0 downto 0);
        dia_r           : in     vl_logic_vector;
        dia_i           : in     vl_logic_vector;
        ena_x           : in     vl_logic;
        wea_x           : in     vl_logic;
        wex_dmem_tms    : in     vl_logic;
        wey_dmem_tms    : in     vl_logic;
        addra           : in     vl_logic_vector;
        addra_dmem      : in     vl_logic_vector;
        addra_x_dmem    : in     vl_logic_vector;
        addra_y_dmem    : in     vl_logic_vector;
        xn_re           : in     vl_logic_vector;
        xn_im           : in     vl_logic_vector;
        web_x           : in     vl_logic;
        we_dmem_dms     : in     vl_logic;
        usr_loading_addr: in     vl_logic;
        d_a_dmem_dms_sel: in     vl_logic;
        address_select_dms: in     vl_logic_vector(0 downto 0);
        addrb_dmem_dms  : in     vl_logic_vector;
        addrb_dmem_tms  : in     vl_logic_vector;
        address_select  : in     vl_logic_vector(1 downto 0);
        ena_y           : in     vl_logic;
        wea_y           : in     vl_logic;
        web_y           : in     vl_logic;
        mem_outr        : out    vl_logic_vector;
        mem_outi        : out    vl_logic_vector
    );
end vfft32_working_memory_v2_0;