_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity eq_compare_v2 is
    generic(
        c_width         : integer := 6;
        c_enable_rlocs  : integer := 1;
        no              : integer := 0;
        yes             : integer := 1;
        zero            : integer := 0
    );
    port(
        a               : in     vl_logic_vector;
        b               : in     vl_logic_vector;
        eq              : out    vl_logic
    );
end eq_compare_v2;