_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity vfft32_dmem_wkg_r_i_v2_0 is
    generic(
        b               : integer := 12;
        points_power    : integer := 5
    );
    port(
        a               : in     vl_logic_vector;
        we              : in     vl_logic;
        d_re            : in     vl_logic_vector;
        d_im            : in     vl_logic_vector;
        clk             : in     vl_logic;
        dpra            : in     vl_logic_vector;
        qdpo_re         : out    vl_logic_vector;
        qdpo_im         : out    vl_logic_vector
    );
end vfft32_dmem_wkg_r_i_v2_0;