_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity c_da_fir_v1_0 is
    generic(
        c_baat          : integer := 1;
        c_channels      : integer := 1;
        c_coeff_type    : integer := 1;
        c_coeff_width   : integer := 4;
        c_data_type     : integer := 1;
        c_data_width    : integer := 4;
        c_enable_rlocs  : integer := 0;
        c_filter_type   : integer := 0;
        c_has_ce        : integer := 1;
        c_has_coeff     : integer := 0;
        c_has_coeff_ld  : integer := 0;
        c_has_sel_i     : integer := 0;
        c_has_sel_o     : integer := 0;
        c_has_sin_f     : integer := 0;
        c_has_sin_r     : integer := 0;
        c_has_sout_f    : integer := 1;
        c_has_sout_r    : integer := 0;
        c_latency       : integer := 4;
        c_mem_init_file : string  := "test.mif";
        c_optimize      : integer := 0;
        c_polyphase_factor: integer := 2;
        c_reg_output    : integer := 0;
        c_reload        : integer := 0;
        c_response      : integer := 1;
        c_result_width  : integer := 12;
        c_saturate      : integer := 0;
        c_shape         : integer := 0;
        c_taps          : integer := 4;
        c_use_model_func: integer := 1;
        c_zpf           : integer := 2;
        back_data       : integer := 20
    );
    port(
        din             : in     vl_logic_vector;
        nd              : in     vl_logic;
        clk             : in     vl_logic;
        ce              : in     vl_logic;
        dout            : out    vl_logic_vector;
        dout_i          : out    vl_logic_vector;
        dout_q          : out    vl_logic_vector;
        rdy             : out    vl_logic;
        rfd             : out    vl_logic;
        sel_i           : out    vl_logic_vector;
        sel_o           : out    vl_logic_vector
    );
end c_da_fir_v1_0;